Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 623

13.3.3.27 PCI Power Management Register 0 (PCIPMR0)
The PCI power management register 0 (PCIPMR0), shown in
management policies to implement in the system.
Offset 0x80
31
R PME_Support
W
Reset 0 1 1 1
15
R
W
Reset 0 0 0 0
Table 13-43 describes the PCIPMR0 fields.
Bits Name
31–27 PME_Support
26 D2_Support
25 D1_Support
24–22 Aux_Current
21 DSI
20 —
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
27 26
D2_Support D1_Support
1 1
NEXT_CAP_PTR
0 0
Figure 13-45. PCI Power Management Register 0 (PCIPMR0)
Table 13-43. PCIPMR0 Field Descriptions
Indicates the power states in which the PCI Controller may assert PME#.
PME_Support (bit 27):
0 PME# cannot be asserted from D0
1 PME# can be asserted from D0
PME_Support (bit 28):
0 PME# cannot be asserted from D1
1 PME# can be asserted from D1
PME_Support (bit 29):
0 PME# cannot be asserted from D2
1 PME# can be asserted from D2
PME_Support (bit 30):
0 PME# cannot be asserted from D3_hot
1 PME# can be asserted from D3_hot
PME_Support (bit 31):
0 PME# cannot be asserted from D3_cold
1 PME# can be asserted from D3_cold
D2 power management state support
0 The PCI controller does not support D2 power management state.
1 The PCI controller supports the D2 power management state.
D1 power management state support
0 The PCI controller does not support D1 power management state.
1 The PCI controller supports the D1 power management state.
Reports the 3.3 Vaux auxiliary current requirements
Device specific initialization. Indicates whether special initialization of this PCI controller is
required.
Reserved
Figure
25 24 22
Aux_Current
1 0 0 0
8 7
0 0 0 0
Description
13-45, indicates the power
Access: Read only
21 20 19 18
DSI — PME_Clock
1 0 1 0
CAP_ID
0 0 0 0
PCI Bus Interface
16
Version
1 1
0
0 1
13-41