Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 412

DDR Memory Controller
Bits Name
19–21 WR_DATA_DELAY Write command to write data strobe timing adjustment. Controls the amount of delay applied to the
22 —
23–25 CKE_PLS
26–31 FOUR_ACT
1
For CPO decodings other than 00000 and 11111, 'READ_LAT' is rounded up to the next integer value.
9.4.1.7 DDR SDRAM Control Configuration (DDR_SDRAM_CFG)
The DDR SDRAM control configuration register, shown in
specifies certain operating features such as self refreshing, error checking and correcting, registered
DIMMs, and dynamic power management.
Offset 0x110
0 1
R
MEM_EN SREN
W
Reset 0 0
16 17
R
2T_EN
W
Reset
Figure 9-8. DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
9-18
Table 9-11. TIMING_CFG_2 Field Descriptions (continued)
data and data strobes for writes. See
details.
000 0 clock delay
001 1/4 clock delay
010 1/2 clock delay
011 3/4 clock delay
Reserved
Minimum CKE pulse width (t
000 Reserved
001 1 cycle
010 2 cycles
Window for four activates (t
to 000001 for DDR1.
000000 Reserved
000001 1 cycle
000010 2 cycles
000011 3 cycles
000100 4 cycles
2 3 4 5
— RD_EN — SDRAM_TYPE
0 0 0 0
BA_INTLV_CTL
Description
Section 9.5.7, "DDR SDRAM Write Timing Adjustments,"
100 1 clock delay
101 5/4 clock delay
110 3/2 clock delay
111 Reserved
)Can be set to 001 for DDR1.
CKE
011 3 cycles
100 4 cycles
101–111 Reserved
). This is applied to DDR2 with eight logical banks only. Must be set
FAW
...
01001119 cycles
010100 20 cycles
010101–111111 Reserved
Figure 9-8, enables the interface logic and
7 8 9 10
— DYN_PWR
1 0 0 0 0
23 24 25 26
— x32_EN
All zeros
Access: Read/Write
11 12 13
DBW 8_BE
0 0 0
27 28 29
PCHB8 HSE — MEM_HALT
Freescale Semiconductor
for
14 15
NCAP —
0 0
30 31
BI