Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 334

e300 Processor Core Overview
The following sections describe the e300-core-implementation-specific features as they apply to registers.
7.3.1.1 UISA Registers
UISA registers are user-level registers that include the following.
7.3.1.1.1 General-Purpose Registers (GPRs)
The PowerPC architecture defines 32 user-level GPRs that are 32 bits wide in 32-bit cores. The GPRs serve
as the data source or destination for all integer instructions.
7.3.1.1.2 Floating-Point Registers (FPRs)
The PowerPC architecture also defines 32 user-level, 64-bit FPRs. The FPRs serve as the data source or
destination for floating-point instructions. These registers can contain data objects of either single- or
double-precision floating-point formats.
7.3.1.1.3 Condition Register (CR)
The CR is a 32-bit user-level register that provides a mechanism for testing and branching. It consists of
eight 4-bit fields that reflect the results of certain operations, such as move, integer and floating-point
comparisons, arithmetic, and logical operations.
7.3.1.1.4 Floating-Point Status and Control Register (FPSCR)
The user-level FPSCR contains all floating-point exception signal bits, exception summary bits, exception
enable bits, and rounding control bits needed for compliance with the IEEE 754 standard.
7.3.1.1.5 User-Level SPRs
The PowerPC architecture defines numerous special purpose registers that serve a variety of functions,
such as providing controls, indicating status, configuring the core, and performing special operations.
During normal execution, a program can access the registers, as shown in
program's access privilege (supervisor or user, determined by the privilege-level bit, MSR[PR]). Note that
GPRs and FPRs are accessed through operands that are part of the instructions. Access to registers can be
explicit (that is, through the use of specific instructions for that purpose such as Move to Special-Purpose
Register (mtspr) and Move from Special-Purpose Register (mfspr) instructions) or implicit, as the part of
the execution of an instruction. Some registers are accessed both explicitly and implicitly. In the e300 core,
all SPRs are 32 bits wide.
The following SPRs are accessible by user-level software:
• Link register (LR)—The LR can be used to provide the branch target address and to hold the return
address after branch and link instructions. The LR is 32 bits wide in 32-bit implementations.
• Count register (CTR)—The CTR is decremented and tested automatically as a result of
branch-and-count instructions. The CTR is 32 bits wide in 32-bit implementations.
• XER register—The 32-bit XER contains the summary overflow bit, integer carry bit, overflow bit,
and a field specifying the number of bytes to be transferred by a Load String Word Indexed (lswx)
or Store String Word Indexed (stswx) instruction.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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Figure 7-2, depending on the
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