Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 573

12.3.8.4 DMA Source Address Register (DMASAR n )
DMASARn indicates the address from which the DMA controller will be reading data. The software must
ensure that this is a valid memory address.
Offset 0x110, 0x190, 0x210, 0x290
31
R
W
Reset
Table 12-13 describes the DMASARn register.
Bits Name
31–0 SA Source address of DMA transfer. The content of this field is updated after each DMA read operation.
12.3.8.5 DMA Destination Address Register (DMADAR n )
DMADARn indicates the address to which the DMA controller will be writing data. The software must
ensure that this is a valid memory address.
Offset 0x118, 0x198, 0x218, 0x298
31
R
W
Reset
Table 12-14 describes the DMADARn register.
Bits Name
31–0 DA Destination address of DMA transfer.Updated after each DMA write operation.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Figure 12-13
Figure 12-13. DMA Source Address Register (DMASAR n )
Table 12-13. DMASAR n Field Descriptions
Figure 12-14
Figure 12-14. DMA Destination Address Register (DMADAR n )
Table 12-14. DMASAR n Field Descriptions
shows the DMASARn.
SA
All zeros
Description
shows the DMADARn fields.
DA
All zeros
Description
DMA/Messaging Unit
Access: User Read/Write
0
Access: User Read/Write
0
12-13