Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 432

DDR Memory Controller
amount of data transferred is determined by the data masks and the burst size, which is set to four
by the DDR memory controller.
• Refresh (similar to MCAS before MRAS)—Causes a row to be read in all logical banks (JEDEC
SDRAM) as determined by the refresh row address counter. This refresh row address counter is
internal to the SDRAM. After being read, the row is automatically rewritten in the memory array.
All logical banks must be in a precharged state before executing a refresh. The memory controller
also supports posted refreshes, where several refreshes may be executed at once, and the refresh
interval may be extended.
• Mode register set (for configuration)—Allows setting of DDR SDRAM options. These options are:
MCAS latency, additive latency (for DDR2), write recovery (for DDR2), burst type, and burst
length. MCAS latency may be chosen as provided by the preferred SDRAM (some SDRAMs
provide MCAS latency {1,2,3}, some provide MCAS latency {1,2,3,4,5}, and so on). Burst type
is always sequential. Although some SDRAMs provide burst lengths of 1, 2, 4, 8, and page size,
this memory controller supports a burst length of 4. A burst length of 8 is supported for
DDR1memory only. For DDR2 in 32-bit bus mode, all 32-byte burst accesses from the platform
are split into two 16-byte (that is, 4-beat) accesses to the SDRAMs in the memory controller. The
mode register set command is performed by the DDR memory controller during system
initialization. Parameters such as mode register data, MCAS latency, burst length, and burst type,
are set by software in DDR_SDRAM_MODE[SDMODE] and transferred to the SDRAM array by
the DDR memory controller after DDR_SDRAM_CFG[MEM_EN] is set. If
DDR_SDRAM_CFG[BI] is set to bypass the automatic initialization, then the MODE registers can
be configured through software through use of the DDR_SDRAM_MD_CNTL register.
• Self refresh (for long periods of standby)—Used when the device is in standby for very long
periods of time. Automatically generates internal refresh cycles to keep the data in all memory
banks refreshed. Before execution of this command, the DDR controller places all logical banks in
a precharged state.
CKE
Operation
Prev.
Activate H
Precharge select H
logical bank
Precharge all logical H
banks
Read H
Read with H
auto-precharge
Write H
Write with H
auto-precharge
Mode register set H
Auto refresh H
Self refresh H
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
9-38
Table 9-30. DDR SDRAM Command Table
CKE
MCS MRAS MCAS
Current
H L L
H L L
H L L
H L H
H L H
H L H
H L H
H L L
H L L
L L L
MWE MBA
H H Logical bank select
H L Logical bank select
H L X
L H Logical bank select
L H Logical bank select
L L Logical bank select
L L Logical bank select
L L Opcode
L H X
L H X
MA10 MA
Row Row
L X
H X
L Column
H Column
L Column
H Column
Opcode Opcode and mode
X X
X X
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