Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 612

PCI Bus Interface
13.3.3.5 Revision ID Configuration Register
Figure 13-23 shows the revision ID fields.
Offset 08
7
R
W
Reset
Table 13-27 shows the bit settings of the revision ID register.
Table 13-27. Revision ID Configuration Register Field Descriptions
Bits Name
7–0 RID
13.3.3.6 Standard Programming Interface Configuration Register
Figure 13-24 shows the standard programming interface fields. This is the lower byte of the class code.
Offset 09
7
R
W
Reset
Figure 13-24. Standard Programming Interface Configuration Register
Table 13-28 shows the bit settings of the standard programming interface register.
Table 13-28. Standard Programming Interface Configuration Register Field Descriptions
Bits Name
7–0 PI
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
13-30
Figure 13-23. Revision ID Configuration Register
Revision ID. Specifies a revision code of the PCI controller.
8'h21 Revision 021.
Programming interface. This field is hard-wired to 0x00.
RID
Revision-dependent
Description
PI
All zeros
Description
Access: Read-only
0
Access: Read-only
0
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