Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 749

Bits Name
30 DPEDIS Data parity error disable.
0 Allow eTSEC to report IEVENT[DPE] status.
1 Do not set IEVENT[DPE] if a parity error occurs in eTSEC's FIFO or filer arrays.
31 PERRDIS Receive frame parse error disable.
0 Allow eTSEC to report IEVENT[PERR] status.
1 Do not set IEVENT[PERR] if a parse error occurs on a received frame.
15.5.3.1.6 Ethernet Control Register (ECNTRL)
ECNTRL is a register writable by the user to reset, configure, and initialize the eTSEC. Note that the
FIFM, GMIIM, RPM, and RMM fields are read-only, having been set after sampling signals at
power-on-reset. (Refer to the TSEC mode
(RCWHR)").
Figure 15-7 describes the definition for the ECNTRL register.
Offset eTSEC1:0x2_4020; eTSEC2:0x2_5020
0
R
W
Reset
16 17
R FIFM
CLRCNT AUTOZ STEN
W
Reset
Table 15-11 describes the fields of the ECNTRL register.
Bits Name
0–15 — Reserved
16 FIFM FIFO mode. Not supported.
17 CLRCNT Clear all statistics counters
0 Allow MIB counters to continue to increment.
1 Reset all MIB counters.
This bit is self-resetting.
18 AUTOZ Automatically zero MIB counter values.
0 The user must write the addressed counter zero after a host read.
1 The addressed counter value is automatically cleared to zero after a host read.
This is a steady state signal and must be set prior to enabling the Ethernet controller and must not be
changed without proper care.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-10. EDIS Field Descriptions (continued)
inSection 4.3.2.2, "Reset Configuration Word High Register
18 19 20
Figure 15-7. ECNTRL Register Definition
Table 15-11. ECNTRL Field Descriptions
Description
—
All zeros
24 25
GMIIM TBIM RPM
—
All zeros
Description
Enhanced Three-Speed Ethernet Controllers
26 27 28 29
RMM SGMIIM
R100M
Access: Mixed
15
30 31
—
15-31