Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 263

5.7.5.1 Global Timers Configuration Registers (GTCFR n )
The global timers configuration registers (GTCFR1 and GTCFR2), shown in
contain configuration parameters used by the timers. These registers allow simultaneous starting, stopping
and resetting of a pair of timers (1 and 2 or 3 and 4) or of a groups of timers (1, 2, 3, and 4) if one bus cycle
is used. GTCFR is cleared by reset.
For proper operation of the timers, do not change the modes of operation and
enable the timer in the same register write operation. The modes can be
changed when GTCFRn[RSTn] is cleared. However, when GTCFRn[RSTn]
are set, they are the only bits that can be changed.
Offset 0x00
0
R
PCAS
W
Reset
Figure 5-40. Global Timers Configuration Register 1 (GTCFR1)
Table 5-57 defines the bit fields of GTCFR1.
Bits Name
0 PCAS Pair-cascade mode
0 Normal operation
1 Timers 1 and 2 cascade to form a 32-bit timer.
Note: This bit is ignored in super-cascade mode (GTCFR2[SCAS] = 1).
Note: It is allowed to change the value of this bit only when the corresponding timers are in reset mode.
1 BCM Backward compatible mode
0 Provide backward compatibility to PowerQUICC II family timers. In this mode GTCFR1[GM2] bit will
control the gate mode for timers 1 and 2 and GTCFR2[GM4] bit will control the gate mode for timers 3
and 4. GTCFR1[GM1] and GTCFR2[GM3] bits are ignored.
1 Normal operational mode
2 STP2 Stop timer 2
0 Normal operation
1 Reduce power consumption of the corresponding timer. This bit stops all clocks to the timer 2, except the
Register Interface clock, which allows to read and write timer registers. The clocks to the timer remain
stopped until the user clears this bit or a hardware reset occurs.
3 RST2 Reset timer 2
0 Reset the timer 2, including GTMDR2, GTRFR2, GTCNR2, GTCPR2, and GTEVR2 (a software reset is
identical to an external reset).
1 Enable the corresponding timer if the STP2 bit is cleared.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
1 2
BCM STP2
Table 5-57. GTCFR1 Bit Settings
Thus, the user should first clear the RST1 and RST2 bits (without changing PCAS) and then, in a
separate write to the register, change the value of PCAS.
NOTE
3 4
RST2 GM2
All zeros
Description
System Configuration
Figure 5-40 and Figure
Access: Read/Write
5 6
GM1 STP1
5-41,
7
RST1
5-55