Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 11

Paragraph
Number
7.3.1.1.1
7.3.1.1.2
7.3.1.1.3
7.3.1.1.4
7.3.1.1.5
7.3.1.2 VEA Registers ....................................................................................................... 7-17
7.3.1.3 OEA Registers ....................................................................................................... 7-17
7.3.1.3.1
7.3.1.3.2
7.3.1.3.3
7.3.2 Instruction Set and Addressing Modes ...................................................................... 7-26
7.3.2.1 PowerPC Instruction Set and Addressing Modes.................................................. 7-26
7.3.2.2 Implementation-Specific Instruction Set ............................................................... 7-27
7.3.3 Cache Implementation ............................................................................................... 7-28
7.3.3.1 PowerPC Cache Characteristics ............................................................................ 7-28
7.3.3.2 Implementation-Specific Cache Organization....................................................... 7-28
7.3.3.3 Instruction and Data Cache Way-Locking............................................................. 7-30
7.3.4 Interrupt Model .......................................................................................................... 7-30
7.3.4.1 PowerPC Interrupt Model...................................................................................... 7-30
7.3.4.2 Implementation-Specific Interrupt Model ............................................................. 7-31
7.3.5 Memory Management................................................................................................ 7-34
7.3.5.1 PowerPC Memory Management............................................................................ 7-34
7.3.5.2 Implementation-Specific Memory Management ................................................... 7-34
7.3.6 Instruction Timing ..................................................................................................... 7-35
7.3.7 Core Interface ............................................................................................................ 7-36
7.3.7.1 Memory Accesses.................................................................................................. 7-37
7.3.7.2 Signals.................................................................................................................... 7-37
7.3.8 Debug Features ......................................................................................................... 7-38
7.3.8.1 Breakpoint Signaling ............................................................................................. 7-38
7.4 Differences Between Cores........................................................................................... 7-39
Integrated Programmable Interrupt Controller (IPIC)
8.1 Introduction...................................................................................................................... 8-1
8.2 Features ............................................................................................................................ 8-4
8.3 Modes of Operation ......................................................................................................... 8-4
8.3.1 Core Enable Mode ....................................................................................................... 8-4
8.3.2 Core Disable Mode ...................................................................................................... 8-5
8.4 External Signal Description ............................................................................................. 8-5
8.4.1 Overview...................................................................................................................... 8-5
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Contents
General-Purpose Registers (GPRs) ................................................................... 7-16
Floating-Point Registers (FPRs)........................................................................ 7-16
Condition Register (CR).................................................................................... 7-16
Floating-Point Status and Control Register (FPSCR) ....................................... 7-16
User-Level SPRs................................................................................................ 7-16
Machine State Register (MSR).......................................................................... 7-17
Segment Registers (SRs) ................................................................................... 7-19
Supervisor-Level SPRs...................................................................................... 7-19
Title
Chapter 8
Page
Number
xi