Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 831

coalescing that may be specified in TXIC/RXIC. Software may poll this register at any time to check for
pending interrupts. If an event occurs and its corresponding enable bit is set in the event mask register
(TEMASK), the event also causes a hardware interrupt at the PIC. A bit in the timer event register is
cleared by writing a 1 to that bit position. Figure 15-4 describes the definition for the TMR_TEVENT
register.
Offset eTSEC1:0x2_4E04
0
R
W
Reset
16
R
W
Reset
Table 15-110 describes the fields of the TMR_TEVENT register fields for the timer.
Bits Name
0–6 — Reserved
6 ETS2 External trigger 2 timestamp sampled
0 external trigger timestamp not sampled
1 external trigger timestamp sampled
7 ETS1 External trigger 1 timestamp sampled
0 external trigger timestamp not sampled
1 external trigger timestamp sampled
8–13 — Reserved
14 ALM2 Current time equaled alarm time register 2
0 alarm time has not be reached yet
1 alarm time has been reached
15 ALM1 Current time equaled alarm time register 1
0 alarm time has not be reached yet
1 alarm time has been reached
16–23 — Reserved
24 PP1 Indicates that a periodic pulse has been generated based on FIPER1 register.
0 periodic pulse not generated
1 periodic pulse generated
25 PP2 Indicates that a periodic pulse has been generated based on FIPER2 register.
0 periodic pulse not generated
1 periodic pulse generated
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
5
—
—
Figure 15-106. TMR_TEVENT Register Definition
Table 15-110. TMR_TEVENT Register Field Descriptions
Enhanced Three-Speed Ethernet Controllers
6 7 8
ETS2 ETS1
All zeros
23 24 25
PP1 PP2 PP3
All zeros
Description
Access: W1C
13 14
— ALM2 ALM1
26 27
—
15
31
15-113