Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 910

Enhanced Three-Speed Ethernet Controllers
Table 15-164. Receive Buffer Descriptor Field Descriptions (continued)
Offset Bits Name
0–1 8 BC Broadcast. Written by the eTSEC. (Only valid if L is set.) Is set if the DA is broadcast
(FF-FF-FF-FF-FF-FF).
9 MC Multicast. Written by the eTSEC. (Only valid if L is set.) Is set if the DA is multicast and not BC.
10 LG Rx frame length violation, written by the eTSEC (only valid if L is set).
A frame length greater than or equal to the maximum frame length was recognized; in this case LG is
set regardless of the setting of MACCFG2[Huge Frame]. If MACCFG2[Huge Frame] is cleared, the
frame is truncated to the value programmed in the maximum frame length register. This bit is valid only
if the L bit is set.
11 NO Rx non-octet aligned frame, written by the eTSEC (only valid if L is set).
A frame that contained a number of bits not divisible by eight was received.
12 SH Short frame, written by the eTSEC (only valid if L is set). A frame length less than the minimum 64B
that is defined for ethernet. was recognized, provided RCTRL[RSF] is set.
13 CR Rx CRC error, written by the eTSEC (only valid if L is set).
This frame contains a CRC error and is an integral number of octets in length.This bit is also set if a
receive code group error is detected.
14 OV Overrun, written by the eTSEC (only valid if L is set).
A receive FIFO overrun occurred during frame reception. If this bit is set, the other status bits, M, LG,
NO, CR and TR lose their normal meaning and are zero.
15 TR Truncation, written by the eTSEC (only valid if L is set).
Set if the receive frame is truncated. This can happen if a frame length greater than the maximum
frame length is received and MACCFG2[Huge Frame] is cleared. If this bit is set, the frame must be
discarded and the other error bits must be ignored as they may be incorrect.
2–3 0–15 Data Data length, written by the eTSEC.
Length Data length is the number of octets written by the eTSEC into this BD's data buffer if L is cleared (the
value is equal to MRBLR), or, if L is set, the length of the frame including CRC, FCB (if
RCTRL[PRSDEP > 00), preamble (if MACCFG2[PreAmRxEn]=1), timestamp (if RCTRL[TS]=1) and
any padding (RCTRL[PAL]).
4–7 0–31 RX Data Receive buffer pointer, written by the user.
Buffer The receive buffer pointer, which always points to the first location of the associated data buffer, must
be 8-byte aligned. For best performance, use 64-byte aligned receive buffer pointer addresses. The
Pointer
buffer must reside in memory external to the eTSEC.
15.7 Initialization/Application Information
15.7.1 Interface Mode Configuration
This section describes how to configure the eTSEC in different supported interface modes. These include
the following:
• MII
• RMII
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-192
Description
Freescale Semiconductor