Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 70

Table
Number
16-71 Summary siTD Split Transaction State............................................................................. 16-115
16-72 Example Case 2a—Software Scheduling siTDs for an IN Endpoint................................ 16-116
16-73 Summary of Transaction Errors ........................................................................................ 16-119
16-74 Summary Behavior on Host System Errors ...................................................................... 16-122
16-75 Endpoint Capabilities/Characteristics ............................................................................... 16-124
16-76 Current dTD Pointer.......................................................................................................... 16-125
16-77 Multiple Mode Control ..................................................................................................... 16-126
16-78 Next dTD Pointer .............................................................................................................. 16-126
16-79 dTD Token ........................................................................................................................ 16-127
16-80 Buffer Pointer Page 0 ........................................................................................................ 16-127
16-81 Buffer Pointer Page 1 ........................................................................................................ 16-128
16-82 Buffer Pointer Pages 2–4 .................................................................................................. 16-128
16-83 Device Controller State Information Bits ......................................................................... 16-130
16-84 Device Controller Endpoint Initialization......................................................................... 16-133
16-85 Device Controller Stall Response Matrix ......................................................................... 16-134
16-86 Variable Length Transfer Protocol Example (ZLT = 0) .................................................... 16-136
16-87 Variable Length Transfer Protocol Example (ZLT = 1) .................................................... 16-136
16-88 Interrupt/Bulk Endpoint Bus Response Matrix................................................................. 16-137
16-89 Control Endpoint Bus Response Matrix ........................................................................... 16-139
16-90 Isochronous Endpoint Bus Response Matrix .................................................................... 16-142
16-91 Device Error Matrix .......................................................................................................... 16-146
16-92 Error Descriptions ............................................................................................................. 16-147
16-93 Interrupt Handling Order .................................................................................................. 16-147
16-94 Low Frequency Interrupt Events....................................................................................... 16-148
16-95 Error Interrupt Events ....................................................................................................... 16-148
16-96 Functional Differences Between EHCI and EHCI with Embedded TT ........................... 16-149
16-97 Emulated Handshakes ....................................................................................................... 16-151
16-98 ULPI Timing ..................................................................................................................... 16-154
2
17-1 I C Interface Signal Descriptions ......................................................................................... 17-3
2
17-2 I C Interface Signals—Detailed Signal Descriptions ........................................................... 17-4
2
17-3 I C Memory Map .................................................................................................................. 17-4
17-4 I2CnADR Field Descriptions................................................................................................ 17-5
17-5 I2Cn FDR Field Descriptions ............................................................................................... 17-6
17-6 I2CnCR Field Descriptions ................................................................................................... 17-7
17-7 I2CnSR Field Descriptions ................................................................................................... 17-8
17-8 I2CnDR Field Descriptions................................................................................................... 17-9
17-9 I2CnDFSRR Field Descriptions.......................................................................................... 17-10
18-1 DUART Signal Overview ..................................................................................................... 18-3
18-2 DUART Signals—Detailed Signal Descriptions .................................................................. 18-3
18-3 DUART Register Summary .................................................................................................. 18-4
18-4 URBR Field Descriptions ..................................................................................................... 18-6
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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Freescale Semiconductor