Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 726

Enhanced Three-Speed Ethernet Controllers
Table 15-1. eTSEC n Network Interface Signal Properties (continued)
Signal Name
TXA/TXA Serial transmitter, lane A, positive data (and negative data, complement)
RXA/RXA Serial receiver, lane A, positive data (and negative data, complement)
15.4.1 Detailed Signal Descriptions
Below is a description of the eTSEC interface signals. For RGMII mode details please refer to the
Hewlett-Packard reduced gigabit media-independent interface (RGMII) specification version 1.2a, dated
9/22/2000. RMII mode details follow the RMII Consortium Specification, dated 3/20/1998. All other
modes follow the IEEE 802.3 standard, 2000 Edition. Input signals not used are internally disabled. Except
for TSECn_GTX_CLK, output signals not used are driven low.
Signal I/O
TSEC n _COL
TSEC n _CRS
TSEC n _GTX_CLK O
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-8
Table 15-2. eTSEC Signals—Detailed Signal Descriptions
I Collision input. The behavior of this signal is not specified while in full-duplex mode.
State Asserted/Negated—In MII mode, this signal is asserted upon detection of a collision,
Meaning and must remain asserted while the collision persists.
This signal is not used in the following modes:
• RMII
• RTBI
• RGMII
Timing Asserted/Negated—This signal is not required to transition synchronously with
TSEC n _TX_CLK or TSEC n _RX_CLK.
I Carrier sense input. In RTBI mode, this signal is used as SDET (signal detect). In RTBI mode
SDET is tied high internally.
This signal is not used in the following modes:
• RMII
• RGMII
State Asserted/Negated—In MII mode, TSEC n _CRS is asserted while the transmit or
Meaning receive medium is not idle. In the event of a collision, TSEC n _CRS must remain
asserted for the duration of the collision.
Timing Asserted/Negated—This signal is not required to transition synchronously with
TSEC n _TX_CLK or TSEC n _RX_CLK.
Gigabit transmit clock. This signal is an output from the eTSEC into the PHY. TSEC n _GTX_CLK
is a 125-MHz clock that provides a timing reference for TX_EN, TXD, and TX_ER in the following
modes:
• RTBI
In RGMII mode, TSEC n _GTX_CLK becomes the transmit clock and provides timing reference
during 1000Base-T (125 MHz), 100Base-T (25 MHz) and 10Base-T (2.5 MHz) transmissions.
This signal feeds back the uninverted transmit clock in MII mode, but feeds back an inverted
transmit clock in RTBI or RGMII modes.
This signal is driven low unless transmission is enabled.
Function
Description
Reset
State
—
—
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