Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 457

Table 10-3. Enhanced Local Bus Controller Registers (continued)
Offset
0x0B8 LTEIR—Transfer error interrupt register
0x0BC LTEATR—Transfer error attributes register
0x0C0 LTEAR—Transfer error address register
0x0C4 LTECCR—Transfer error ECC register
0x0C8– Reserved
0x0CC
0x0D0 LBCR—Configuration register
0x0D4 LCRR—Clock ratio register
0x0D8– Reserved
0x0DC
0x0E0 FMR—Flash mode register
0x0E4 FIR—Flash instruction register
0x0E8 FCR—Flash command register
0x0EC FBAR—Flash block address register
0x0F0 FPAR—Flash page address register
0x0F4 FBCR—Flash byte count register
0x0F8– Reserved
0x0FC
0x100 FECC0—Flash ECC block 0 register
0x104 FECC1—Flash ECC block 1 register
0x108 FECC2—Flash ECC block 2 register
0x10C FECC3—Flash ECC block 3 register
10.3.1 Register Descriptions
This section provides a detailed description of the eLBC configuration, status, and control registers with
detailed bit and field descriptions.
Address offsets in the eLBC address range that are not defined in
reading or writing. Similarly, only zero should be written to reserved bits of defined registers, as writing
ones can have unpredictable results in some cases.
Bits designated as write-one-to-clear are cleared only by writing ones to them. Writing zeros to them has
no effect.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Enhanced Local Bus Controller
Register
—Block Base Address 0x0_5000
Access
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
w1c 0x0000_0000
—
R/W 0x0004_0000
R/W 0x8000_0008
—
R/W 0x0000_0 n 00
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
—
R 0x0000_0000
R 0x0000_0000
R 0x0000_0000
R 0x0000_0000
Table 10-3
Enhanced Local Bus Controller
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should not be accessed for
10-9