Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 832

Enhanced Three-Speed Ethernet Controllers
Table 15-110. TMR_TEVENT Register Field Descriptions (continued)
Bits Name
26 PP3 Indicates that a periodic pulse has been generated based on FIPER3 register.
0 periodic pulse not generated
1 periodic pulse generated
27–31 — Reserved
15.5.3.10.3 Timer Event Mask Register (TMR_TEMASK)
Timer event mask register. The event mask register provides control over which possible interrupt events
in the TMR_TEVENT register are permitted to participate in generating hardware interrupts to the PIC.
All implemented bits in this register are R/W and cleared upon a hardware reset. Figure 15-111 describes
the definition for the TMR_TEMASK register.
Offset eTSEC1:0x2_4E08
0
R
—
W
Reset
16
R
W
Reset
Table 15-112 describes the fields of the TMR_TEMASK register fields for the timer.
Bits Name
0–5 — Reserved
6 ETS2EN External trigger 2 timestamp sample event enable
7 ETS1EN External trigger 1 timestamp sample event enable
8–13 — Reserved
14 ALM2EN Timer ALM1 event enable
15 ALM1EN Timer ALM2 event enable
16–23 — Reserved
24 PP1EN Periodic pulse event 1 enable
25 PP2EN Periodic pulse event 2 enable
26–31 — Reserved
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-114
5 6
ETS2EN ETS1EN
—
Table 15-111. TMR_TEMASK Register Definition
Table 15-112. TMR_TEMASK Register Field Descriptions
Description
7 8
—
All zeros
23 24 25 26
PP1EN PP2EN
All zeros
Description
Access: Read/Write
13 14 15
ALM2EN ALM1EN
31
—
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