Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 759

Bits Name
23 TXF7 Transmit frame event occurred on ring 7. Set by the eTSEC if IEVENT[TXF] was set in relation to transmitting
a frame from this ring.
24–31 — Reserved
15.5.3.2.3 Default VLAN Control Word Register (DFVLAN)
This register defines the default value for the VLAN Ethertype and control word when VLAN tags are
automatically inserted by the eTSEC, and no per-frame VLAN data is supplied by software. On receive,
this register defines a customizable VLAN Ethertype for automatic deletion. Note that an Ethertype of
0x8808 (Control Word) is not permitted as a custom VLAN tag. Frames with an Ethertype of 0x8808 are
dropped by the receiver. In the case of frames containing stacked VLAN tags, this register defines the tag
associated with the outer or metropolitan area VLAN.
Offset eTSEC1:0x2_4108; eTSEC2:0x2_5108
0
R
W
Reset 1 0 0 0 0
Table 15-17 describes the fields of the DFVLAN register.
Bits Name
0–15 TAG This is the default Ethertype used to tag VLAN frames. On transmit, this tag is inserted ahead of the VLAN
control word; TAG should be set to 0x8100 for IEEE 802.1Q VLAN. On receive, an Ethertype matching TAG or
an Ethertype of 0x8100 marks a VLAN-tagged frame.
Note that if using DFVLAN to set a custom ethertype (that is, using a value other than 0x8100), packets
received with a custom tag are not counted by any of the RMON counters. Affected counters include TRMGV,
RMCA, RBCA, RXCF, RXPF, RXUO, RALN, RFLR, ROVR, RJBR, TMCA, TBCA, TXPF, TXCF.
16–18 PRI This is the default value used for the IEEE Std. 802.1p frame priority.
19 CFI This is the default value used for the IEEE Std. 802.1Q canonical format indicator.
20–31 VID This is the default value used for the virtual-LAN identifier in VLAN-tagged frames. A value of zero is defined
as the null VLAN, however field PRI may be still set independently.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-16. TSTAT Field Descriptions (continued)
TAG
0 0 1 0 0 0 0 0
Figure 15-12. DFVLAN Register Definition
Table 15-17. DFVLAN Field Descriptions
Enhanced Three-Speed Ethernet Controllers
Description
Figure 15-12 describes the DFVLAN register.
15 16 18 19 20
PRI CFI
0 0 0 0 0 0 0 0
Description
Access: Read/Write
VID
0 0 0 0 0 0 0 0
31
0 0 0
15-41