Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 911

• RGMII
• SGMII
• RTBI
The pinout, the data registers that must be initialized, as well as speed selection options are described.
15.7.1.1 MII Interface Mode
Table 15-165 describes the signal configurations required for MII interface mode.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-165. MII Interface Mode Signal Configuration
eTSEC Signals
Signals I/O
Signals
GTX_CLK O
TX_CLK I
TxD[0] O
TxD[1] O
TxD[2] O
TxD[3] O
TX_EN O
TX_ER O
RX_CLK I
RxD[0] I
RxD[1] I
RxD[2] I
RxD[3] I
RX_DV I
RX_ER I
COL I
CRS I
Sum
MII Interface
Frequency [MHz] 25
Voltage [V] 3.3
No. of
Signals
1
leave unconnected
1 TX_CLK
1 TxD[0]
1 TxD[1]
1 TxD[2]
1 TxD[3]
1 TX_EN
1 TX_ER
1 RX_CLK
1 RxD[0]
1 RxD[1]
1 RxD[2]
1 RxD[3]
1 RX_DV
1 RX_ER
1 COL
1 CRS
17
Sum
Enhanced Three-Speed Ethernet Controllers
No. of
I/O
Signals
I 1
O 1
O 1
O 1
O 1
O 1
O 1
I 1
I 1
I 1
I 1
I 1
I 1
I 1
I 1
I 1
16
15-193