Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 879

15.6.3.1 Frame Control Blocks
Frame control blocks (FCBs) are 8-byte blocks of TOE control and/or status data that are passed between
software (driver and TCP/IP stack) and each eTSEC. A FCB always precedes the frame it applies to, and
is present only when TOE functions are being used. As
points to the initial data buffer and the FCB. The initial data buffer must be at least 8 bytes long to contain
the FCB without breaking it. Custom or received Ethernet preamble sequences also follow the FCB if
preambles are visible.
BD
Figure 15-135. Location of Frame Control Blocks for TOE Parameters
For TxBD rings, FCBs are assumed present when the TxBD[TOE/UN] bit is set by user software. The
eTSEC ignores the TxBD[TOE/UN] bit in all BDs other than those pointing to initial data buffers,
therefore FCBs must not be inserted in second and subsequent data buffers. Since TxBD[TOE/UN] can be
set under software discretion, TOE acceleration for transmit may be applied on a frame-by-frame basis.
In the case of RxBD rings, FCBs are inserted by the eTSEC whenever RCTRL[PRSDEP] is set to a
non-zero value. Only one FCB is inserted per frame, in the buffer pointed to by the RxBD with bit F set.
TOE acceleration for receive is enabled for all frames in this case.
15.6.3.2 Transmit Path Off-Load and Tx PTP Packet Parsing
TOE functions for transmit are defined by the contents of the Tx FCB.
definition for the Tx FCB.
0
Offset + 0 VLN
Offset + 2
Offset + 4
Offset + 6
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
L3OS L4OS
L2 HDR L3 HDR
Frame data, first buffer
FCB
BD BD
(last)
(first)
1 2 3 4 5
IP IP6 TUP UDP CIP CTU NPH
L4OS
Figure 15-136. Transmit Frame Control Block
Figure 15-135
L4 HDR
Frame data, second buffer
BD BD
(last)
6 7 8 9
PHCS
VLCTL
Enhanced Three-Speed Ethernet Controllers
shows, the first BD of each frame
BD ring
Figure 15-136 describes the
10 11 12 13 14
L3OS
15
PTP
15-161