Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 370

Integrated Programmable Interrupt Controller (IPIC)
Table 8-7. SIPNR_H/SIFCR_H/SIMSR_H Bit Assignments (continued)
Table 8-8 defines the bit fields of SIPNR_H.
Bits Name
0–31 INT n Each implemented bit (listed in
received, the interrupt controller sets the corresponding SIPNR bit. When a pending interrupt is handled, the
user clears the SIPNR bit by clearing the corresponding event register bit.
SIPNR bits are read only. Writing to this register has no effect.
Note that the SIPNR bit positions are not changed according to their relative priority.
For unimplemented bits, writes are ignored, read = 0.
SIPNR_L is shown in
Offset 0x0C
0
R
W
Reset
Figure 8-5. System Internal Interrupt Pending Register (SIPNR_L)
Table 8-9 lists implemented SIPNR_L fields. Note that these field assignments are also valid for SIFCR_L
and SIMSR_L.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
8-12
Bits
26
27
28
29
30
31
Table 8-8. SIPNR_H Field Descriptions
Table 8-7) corresponds to an internal interrupt source. When an interrupt is
Figure 8-4.
n (Implemented bits are listed in
INT
Table 8-9. SIPNR_L/SIFCR_L/SIMSR_L Bit Assignments
Bits
0
1
2
3
4
5
6
7
8
9
Field
SEC
eTSEC1 1588 timer
eTSEC2 1588 timer
I2C1
I2C2
SPI
Description
Table
All zeros
Field
RTC SEC
PIT
PCI
—
RTC ALR
MU
SBA
DMA
GTM4
GTM8
Access: Read only
8-9.)
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