Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 816

Enhanced Three-Speed Ethernet Controllers
15.5.3.6.38 Transmit Jabber Frame Counter (TJBR)
Figure 15-89 describes the definition for the TJBR register.
Offset eTSEC1:0x2_4718; eTSEC2:0x2_5718
0
R
W
Reset
Figure 15-89. Transmit Jabber Frame Counter Register Definition
Table 15-93 describes the fields of the TJBR register.
Bits Name
0–19 — Reserved
20–31 TJBR Transmit jabber frame counter. Increments for each oversized transmitted frame with an incorrect
FCS value.
15.5.3.6.39 Transmit FCS Error Counter (TFCS)
Figure 15-90 describes the definition for the TFCS register.
Offset eTSEC1:0x2_471C; eTSEC2:0x2_571C
0
R
W
Reset
Table 15-94 describes the fields of the TFCS register.
Bits Name
0–19 — Reserved
20–31 TFCS Transmit FCS error counter. Increments for every valid sized packet with an incorrect FCS value.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-98
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Table 15-93. TJBR Field Descriptions
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Figure 15-90. Transmit FCS Error Counter Register Definition
Table 15-94. TFCS Field Descriptions
19 20
All zeros
Description
19 20
All zeros
Description
Access: Read/Write
31
TJBR
Access: Read/Write
31
TFCS
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