Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 422

DDR Memory Controller
9.4.1.15 DDR Initialization Address (DDR_INIT_ADDR)
The DDR SDRAM initialization address register, shown in
for the automatic CAS to preamble calibration after POR.
Offset 0x148
0
R
W
Reset
Figure 9-16. DDR Initialization Address Configuration Register (DDR_INIT_ADDR)
Table 9-21 describes the DDR_INIT_ADDR fields.
Bits Name
0–31 INIT_ADDR Initialization address. Represents the address that is used for the automatic CAS to preamble calibration
at POR.
9.4.1.16 DDR IP Block Revision 1 (DDR_IP_REV1)
The DDR IP block revision 1 register, shown in
ID, along with major and minor revision information.
Offset 0xBF8
0
R
W
1
Reset n n n n n
1
For reset values, see Table 9-22
Table 9-22 describes the DDR_IP_REV1 fields.
Bits Name
0–15 IP_ID IP block ID. For the DDR controller, this value is 0x0002.
16–23 IP_MJ Major revision. This is currently set to 0x02.
24–31 IP_MN Minor revision. This is currently set to 0x01.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
9-28
Table 9-21. DDR_INIT_ADDR Field Descriptions
IP_ID
n n n n n n n n
Figure 9-17. DDR IP Block Revision 1 (DDR_IP_REV1)
.
Table 9-22. DDR_IP_REV1 Field Descriptions
Figure 9-16, provides the address that is used
INIT_ADDR
All zeros
Description
Figure 9-17, provides read-only fields with the IP block
15 16
IP_MJ
n n n n n n n n
Description
Access: Read/Write
Access: Read Only
23 24
IP_MN
n n n n n n n n
Freescale Semiconductor
31
31
n n n