Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 31

Paragraph
Number
16.6 Host Operations ........................................................................................................... 16-67
16.6.1 Host Controller Initialization ................................................................................... 16-68
16.6.2 Power Port................................................................................................................ 16-69
16.6.3 Reporting Over-Current ........................................................................................... 16-69
16.6.4 Suspend/Resume...................................................................................................... 16-69
16.6.4.1 Port Suspend/Resume .......................................................................................... 16-70
16.6.5 Schedule Traversal Rules......................................................................................... 16-71
16.6.6 Periodic Schedule Frame Boundaries vs. Bus Frame Boundaries........................... 16-72
16.6.7 Periodic Schedule .................................................................................................... 16-75
16.6.8 Managing Isochronous Transfers Using iTDs ......................................................... 16-76
16.6.8.1 Host Controller Operational Model for iTDs ...................................................... 16-76
16.6.8.2 Software Operational Model for iTDs ................................................................. 16-78
16.6.8.2.1
16.6.9 Asynchronous Schedule........................................................................................... 16-80
16.6.9.1 Adding Queue Heads to Asynchronous Schedule ............................................... 16-81
16.6.9.2 Removing Queue Heads from Asynchronous Schedule...................................... 16-82
16.6.9.3 Empty Asynchronous Schedule Detection .......................................................... 16-84
16.6.9.4 Asynchronous Schedule Traversal: Start Event................................................... 16-85
16.6.9.5 Reclamation Status Bit (USBSTS Register)........................................................ 16-85
16.6.10 Managing Control/Bulk/Interrupt Transfers via Queue Heads................................ 16-85
16.6.10.1 Buffer Pointer List Use for Data Streaming with qTDs ...................................... 16-86
16.6.10.2 Adding Interrupt Queue Heads to the Periodic Schedule.................................... 16-88
16.6.10.3 Managing Transfer Complete Interrupts from Queue Heads .............................. 16-88
16.6.11 Ping Control............................................................................................................. 16-89
16.6.12 Split Transactions..................................................................................................... 16-90
16.6.12.1 Split Transactions for Asynchronous Transfers................................................... 16-90
16.6.12.1.1
16.6.12.1.2
16.6.12.2 Split Transaction Interrupt ................................................................................... 16-92
16.6.12.2.1
16.6.12.2.2
16.6.12.2.3
16.6.12.2.4
16.6.12.2.5
16.6.12.2.6
16.6.12.2.7
16.6.12.2.8
16.6.12.2.9
16.6.12.3 Split Transaction Isochronous ........................................................................... 16-104
16.6.12.3.1
16.6.12.3.2
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Contents
Periodic Scheduling Threshold........................................................................ 16-79
Asynchronous—Do-Start-Split........................................................................ 16-91
Asynchronous—Do-Complete-Split ............................................................... 16-91
Split Transaction Scheduling Mechanisms for Interrupt ................................. 16-92
Host Controller Operational Model for FSTNs ............................................... 16-95
Software Operational Model for FSTNs ......................................................... 16-97
Tracking Split Transaction Progress for Interrupt Transfers ........................... 16-98
Split Transaction Execution State Machine for Interrupt ................................ 16-98
Periodic Interrupt—Do-Start-Split .................................................................. 16-99
Periodic Interrupt—Do-Complete-Split ........................................................ 16-100
Managing the QH[FrameTag] Field .............................................................. 16-103
Rebalancing the Periodic Schedule ............................................................... 16-104
Split Transaction Scheduling Mechanisms for Isochronous ......................... 16-105
Tracking Split Transaction Progress for Isochronous Transfers.................... 16-108
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