Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 202

Reset, Clocking, and Initialization
Table 4-30 defines the bit fields of RPR.
Bits Name
0–31 RCPW Reset control protection word. Prevents unintended software reset requests because of a write to the RCR.
The user should write the value 0x5253_5445 (RSTE in ASCII) to enable. Enable indication appears in the
reset control enable register (RCER[CRE]). Reading this register always returns all zeros.
4.5.1.6 Reset Control Register (RCR)
RCR, shown in Figure
writing to this register, the user must enable it by writing the value 0x5253_5445 to the RPR.
Address 0x0_091C
0
R
W
Reset
16
R
W
Reset
Table 4-31 defines the bit fields of RCR.
Bits Name
0–29 — Reserved, should be cleared.
30 SWHR Software hard reset. Setting this bit causes the device to begin a hard reset flow. This bit returns to its reset
state during the reset sequence, so reading it always returns all zeros.
31 — Reserved. This bit should never be set.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
4-36
Table 4-30. RPR Bit Descriptions
4-11, can be used by software to initiate a soft or hard reset sequence. To allow
Figure 4-11. Reset Control Register (RCR)
Table 4-31. RCR Bit Settings
Description
—
All zeros
—
All zeros
Description
Access: User read/write
15
29 30 31
SWHR —
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