Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 830

Enhanced Three-Speed Ethernet Controllers
Table 15-109. TMR_CTRL Register Field Descriptions (continued)
Bits Name
20 ESFDP External Tx/Rx SFD Polarity.
0 Timestamp on rising edge of external SFD indication.
1 Timestamp on falling edge of external SFD indication.
21 ESFDE External Tx/Rx SFD Enable.
0 Timestamp PTP TX frame based on MAC's SFD indication.
1 Timestamp PTP TX frame based on external SFD indication from PHY.
22 ETEP2 External trigger 2 edge polarity
0 Timestamp on the rising edge of the external trigger
1 Timestamp on the falling edge of the external trigger
23 ETEP1 External trigger 1 edge polarity
0 Timestamp on the rising edge of the external trigger
1 Timestamp on the falling edge of the external trigger
24 COPH Generated clock (TSEC_1588_GCLK) output phase.
0 non-inverted divided clock is output
1 inverted divided clock is output
25 CIPH External oscillator input clock phase.
0 non-inverted frequency tuned timer input clock
1 inverted frequency tuned timer input clock (NOTE: this setting is reserved if CKSEL=01.)
26 TMSR Timer soft reset. When enabled, it resets all the timer registers and state machines.
0 normal operation
1 place entire timer in reset except control and config registers
NOTE: Prior to initiating timer reset (setting TMSR), must gracefully stop receiver (See
MACCFG1[RX_EN] description).
User programmable registers are not reset by the soft reset e.g. TMR_CTRL, TMR_TEMASK,
TMR_PEMASK, TMR_ADD, TMR_PRSC, TMROFF_H/L, TMR_ALARMn, and TMR_FIPERn.
28 BYP Bypass drift compensated clock
0 64-bit clock counter is incremented on the accumulator overflow
1 64-bit clock counter is directly driven from the external oscillator ignoring accumulator overflow
29 TE 1588 timer enable. If not enabled, all the timer registers and state machines are disabled.
0 timer not enabled
1 timer enabled and resume normal operation
30–31 CKSEL 1588 Timer reference clock source select.
00 External high precision timer reference clock (TSEC_TMR_CLK)
01 eTSEC system clock
10 Reserved
11 RTC clock input. Note that the 1588 reference clock must be no slower than 1/7 the Rx_clk
15.5.3.10.2 Timer Event Register (TMR_TEVENT)
The eTSEC precision timer implementation can generate additional interrupts that are independent of the
frame based events that controlled via IEVENT. The timer interrupts are not affected by any interrupt
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-112
frequency.
The default clock select is eTSEC system clock, which is always active when eTSEC is enabled.
The user must ensure the corresponding clock source is active before changing the 1588 refclk
selection to external reference, RTC, or TX clock. Selecting an inactive 1588 reference clock may
cause boundedly undefined behavior in the ethernet controller and on accesses to the 1588
registers.
Description
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