Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 782

Enhanced Three-Speed Ethernet Controllers
Offset eTSEC1:0x2_44C4; eTSEC2:0x2_54C4
0
R
W
Reset
Table 15-39 describes the fields of the TMR_RXTS_H/L register.
Bits Name
0–63 TMR_RXTS_H/L Value of the eTSEC precision timer upon detection of a start of frame symbol for the received frame.
15.5.3.4 MAC Functionality
This section describes the MAC registers and provides a brief overview of the functionality that can be
exercised through the use of these registers, particularly those that provide functionality not explicitly
required by the IEEE 802.3 standard. All of the MAC registers are 32 bits wide.
15.5.3.4.1 Configuring the MAC
The MAC configuration registers 1 and 2 provide for configuring the MAC in multiple ways:
• Adjusting the preamble length—The length of the preamble can be adjusted from the nominal
seven bytes to some other (non-zero) value. Should custom preamble insertion/extraction be
configured, then this register must by left at its default value.
• Varying pad/CRC combinations—Three different pad/CRC combinations are provided to handle a
variety of system requirements. Simplest are frames that already have a valid frame check
sequence (FCS) field. The other two options include appending a valid CRC or padding and then
appending a valid CRC, resulting in a minimum frame of 64 octets. In addition to the
programmable register set, the pad/CRC behavior can be dynamically adjusted on a per-packet
basis.
15.5.3.4.2 Controlling CSMA/CD
The half-duplex register (HAFDUP) allows control over the carrier-sense multiple access/collision
detection (CSMA/CD) logic of the eTSEC. Half-duplex mode is only supported for 10- and 100-Mbps
operation. Following the completion of the packet transmission the part begins timing the inter packet gap
(IPG) as programmed in the back-to-back IPG configuration register. The system is now free to begin
another frame transfer.
In full-duplex mode both the carrier sense (CRS) and collision (COL) indications from the PHY are
ignored, but in half-duplex mode the eTSEC defers to CRS, and following a carrier event, times the IPG
using the non-back-to-back IPG configuration values that include support for the optional
two-thirds/one-third CRS deferral process. This optional IPG mechanism enhances system robustness and
ensures fair access to the medium. During the first two-thirds of the IPG, the IPG timer is cleared if CRS
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-64
TMR_RXTS_H
Figure 15-35. TMR_RXTS_H/L Register Definition
Table 15-39. TMR_RXTS_H/L Register Field Descriptions
31 32
TMR_RXTS_L
All zeros
Description
Access: Read/Write
63
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