Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 439

The auto-refresh commands are staggered across the two possible banks to reduce the system's
instantaneous power requirements. Three sets of auto refresh commands are issued on consecutive cycles
when the memory is populated with one DIMMs. The initial PRECHARGE-ALL commands are also
staggered in three groups for convenience. It is important to note that when entering self-refresh mode,
only one refresh command is issued simultaneously to all physical banks. For this entire refresh sequence,
no cycle optimization occurs for the usual case where fewer than two banks are installed. After the refresh
sequence completes, any pending memory request is initiated after an inactive period specified by
TIMING_CFG_1 [REFREC] and TIMING_CFG_3[EXT_REFREC]. In addition, posted refreshes are
supported to allow the refresh interval to be set to a larger value.
9.5.8.1 DDR SDRAM Refresh Timing
Refresh timing for the DDR SDRAM is controlled by the programmable timing parameter
TIMING_CFG_1 [REFREC], which specifies the number of memory bus clock cycles from the refresh
command until a logical bank activate command is allowed. The DDR memory controller implements
bank staggering for refreshes, as shown in
example).
0
SDRAM Clock
MCKE
MCS(0)
MCS(1)
MRAS
MCAS
MA n
Figure 9-30. DDR SDRAM Bank Staggered Auto Refresh Timing
System software is responsible for optimal configuration of TIMING_CFG_1 [REFREC] and
TIMING_CFG_3[EXT_REFREC] at reset. Configuration must be completed before DDR SDRAM
accesses are attempted.
9.5.8.2 DDR SDRAM Refresh and Power-Saving Modes
In full-on mode, the DDR memory controller supplies the normal auto refresh to SDRAM. In sleep mode,
the DDR memory controller can be configured to take advantage of self-refreshing SDRAMs or to provide
no refresh support. Self-refresh support is enabled with the SREN memory control parameter.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Figure 9-30
1 2 3 4 5
(TIMING_CFG_1 [REFREC] = 10 in this
6 7 8 9 10
REFREC
DDR Memory Controller
11 12
13 14
0 or 3
ROW
9-45