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Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 444

Integrated
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DDR Memory Controller
Table 9-34. Memory Interface Configuration Register Initialization Parameters (continued)
Name
DDR_SDRAM_MODE_2
DDR_SDRAM_INTERVAL Interval configuration
DDR_DATA_INIT
DDR_SDRAM_CLK_CNTL Clock adjust
DDR_INIT_ADDR
9.6.1
Programming Differences Between Memory Types
Depending on the memory type used, certain fields must be programmed differently.
the differences in certain fields for different memory types. Note that this table does not list all fields that
must be programmed.
Table 9-35. Programming Differences Between Memory Types
Parameter
AP n _EN
Chip Select n Auto
Precharge Enable
ODT_RD_CFG
Chip Select ODT Read
Configuration
ODT_WR_CFG
Chip Select ODT Write
Configuration
ODT_PD_EXIT
ODT Powerdown Exit
PRETOACT
Precharge to Activate
Timing
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
9-50
Description
Mode configuration
Data initialization configuration
register
Initialization address
Description
DDR1
DDR2
DDR1
DDR2
DDR1
DDR2
DDR1
DDR2
DDR1
DDR2
Parameter
ESDMODE2
ESDMODE3
REFINT
BSTOPRE
INIT_VALUE
CLK_ADJUST
INIT_ADDR
Differences
Can be used to place chip select n in auto
precharge mode
Can be used to place chip select n in auto
precharge mode
Should always be set to 000
Can be enabled to assert ODT if desired. This
could be set differently depending on system
topology. However, systems with only 1 chip select
typically not uses ODT when issuing reads to the
memory.
Should always be set to 000
Can be enabled to assert ODT if desired. This
could be set differently depending on system
topology. However, ODT typically is set to assert
for the chip select that is getting written to (value
would be set to 001).
Should be set to 0001
Should be set according to the DDR2
specifications for the memory used. The JEDEC
parameter this applies to is t
Should be set according to the specifications for
the memory used (t
)
RP
Should be set according to the specifications for
the memory used (t
)
RP
Section/Page
9.4.1.10/9-23
9.4.1.12/9-26
9.4.1.13/9-27
9.4.1.14/9-27
9.4.1.15/9-28
Table 9-35
illustrates
Section/Page
9.4.1.2/9-10
9.4.1.2/9-10
9.4.1.2/9-10
9.4.1.4/9-12
.
AXPD
9.4.1.5/9-14
Freescale Semiconductor

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