Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 531

10.4.4.4.3 Byte Select Signal Timing (BST
If BR [MSEL] of the accessed memory bank selects a UPM on the currently requested cycle, the selected
n
UPM affects the assertion and negation of the appropriate LBS[0:1] signal. The timing of both byte-select
signals is specified in the RAM word. However, LBS[0:1] are also controlled by the port size of the
accessed bank, the number of bytes to transfer, and the address accessed.
control LBS[0:1].
UPMA
UPMB
UPMC
The uppermost byte select (LBS0), when asserted, indicates that LAD[0:7] contains valid data during a
cycle. Likewise, LBS1 indicates that LAD[8:15] contain valid data. For a UPM refresh timer request, all
LBS[0:1] signals are asserted/negated by the UPM according to the refresh pattern only. Following any
internal bus monitor exception, the LBS[0:1] signals are negated regardless of the exception handling
provided by any UPM exception pattern to prevent spurious writes to external RAM.
10.4.4.4.4 General-Purpose Signals (G
The general-purpose signals (LGPL[0:5]) each have two bits in the RAM word that define the logical value
of the signal to be changed at the rising edge of the bus clock and/or at the falling edge of the bus clock.
LGPL0 offers enhancements beyond the other LGPL
LGPL0 can be controlled by an address line specified in M
should be set in the RAM word. For example, for a SIMM with multiple banks, this address line can be
used to switch between internal memory device banks.
10.4.4.4.5 Loop Control (LOOP)
The LOOP bit in the RAM word specifies the beginning and end of a set of UPM RAM words that are to
be repeated. The first time LOOP = 1, the memory controller recognizes it as a loop start word and loads
the memory loop counter with the corresponding contents of the loop field shown in
RAM word for which LOOP = 1 is recognized as a loop end word. When it is reached, the loop counter is
decremented by one.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
)
n
Bank Selected
BR n [MSEL] BR n [PS]
MUX
Figure 10-66. LBS Signal Selection
T , GO
n n n
lines.
n
Figure 10-66
LA[23:25]
Byte count
Byte-Select
Logic
)
MR[G0CL]. To use this feature, G0H and G0L
x
Enhanced Local Bus Controller
shows how UPMs
LBS0
LBS1
Table 10-41. The next
10-83