Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 177

4.3.1.2 SYS_CLK_IN Division
When the device is configured as a PCI host, the CFG_CLKIN_DIV configuration input selects the
relationship between SYS_CLK_IN and PCI_SYNC_OUT as shown in
device supports threeoutput signals. The frequency of the output clocks will be equal to the
PCI_SYNC_OUT frequency.
When the device is configured as a PCI agent, the CFG_CLKIN_DIV configuration input can be used to
double the internal clock frequencies, if sampled as '0' during power-on reset assertion. This feature is
useful if a fixed internal frequency is desired regardless of whether the PCI clock is running at 33 or
66 MHz. PCI specifications require the PCI clock frequency information to be provided by the M66EN
signal.
When the device is configured as PCI host, there are two scenarios for connecting the CFG_CLKIN_DIV
configuration input. If the frequency of SYS_CLK_IN is 33 MHz (that is, the PCI system is running on a
33-MHz clock), CFG_CLKIN_DIV should be connected high. If the frequency of SYS_CLK_IN is
66 MHz (that is, the PCI system can run at 33- or 66-MHz clock signaled by M66EN), CFG_CLKIN_DIV
should be connected to the M66EN signal.
CFG_CLKIN_DIV
1
0
4.3.1.3 Selecting Reset Configuration Input Signals
The example described in
input signals (CFG_RESET_SOURCE, CFG_CLKIN_DIV). The reset sequence duration is measured
from the negation of PORESET to the negation of HRESET. Note that the duration mentioned in this table
is typical and does not represent cases in which the process of loading the reset configuration word had to
be retried due to errors.
2
I C EEPROM SYS_CLK_IN
Configuration Frequency
Words (Host Mode)
No 33 MHz
No 66 MHz
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 4-6. SYS_CLK_IN Division
In PCI host mode, SYS_CLK_IN: PCI_SYNC_OUT = 1:1 and all PCI_CLK_OUT[0:2] clocks
are running at a frequency which is equal to the SYS_CLK_IN frequency
In PCI agent mode, SYS_CLK_IN: PCI_SYNC_OUT = 2:1 and all PCI_CLK_OUT[0:2] clocks
are running at a frequency which is equal to the PCI_SYNC_OUT frequency.
Table 4-7 shows how the user should pull down or pull up the reset configuration
Table 4-7. Selecting Reset Configuration Input Signals
CFG_CLKIN_DIV
Frequency
(Host Mode)
(Agent Mode)
1
1
Description
PCI_CLK
CFG_RESET_
SOURCE[0:3]
33 MHz 0000
(RCW loaded from NOR
Flash)
66 MHz 1000–1100
(use hard coded RCW)
Reset, Clocking, and Initialization
Table 4-7. As a PCI host, the
Reset Sequence
Duration in
SYS_CLK_IN/
PCI_CLK
Cycles
15210
15380
Duration
μ
456 s
μ
231 s
4-11