Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 203

4.5.1.7 Reset Control Enable Register (RCER)
RCER, shown in Figure
RCR.
Address 0x0_0920
0
R
W
Reset
16
R
W
Reset
Table 4-32 defines the bit fields of RCER.
Bits Name
0–30 — Reserved, should be cleared.
31 CRE Control register enabled. When set, indicates that the RPR was accessed with a value that enables the RCR.
Writing 1 to this bit disables the RCR and clears this bit. Writing zero has no effect.
4.5.2 Clock Configuration Registers
The clock configuration and status registers are shown in
Address
0x0_0A00 System PLL mode register (SPMR)
0x0_0A04 Output clock control register (OCCR)
0x0_0A08 System clock control register (SCCR)
0x0_0A0C– Reserved, should be cleared
0x0_0AFC
4.5.2.1 System PLL Mode Register (SPMR)
SPMR is shown in Figure
input signal and the reset configuration word low loaded during the reset flow. Note that this register is
updated only during a power-on reset sequence and not by a hard reset sequence. It may hold values
different than those in the RCWLR after a a hard reset sequence.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
4-12, indicates by the CRE field that the RPR is accessed with a value that enables
Figure 4-12. Reset Control Enable Register (RCER)
Table 4-32. RCER Bit Settings
Table 4-33. Clock Configuration Registers Memory Map
Register
4-13, gets its values according to the CFG_CLKIN_DIV reset configuration
—
All zeros
—
All zeros
Description
Table 4-33.
Access
R
R/W
R/W 0x7DDF_FFFF
—
Reset, Clocking, and Initialization
Access: User read/write
29 30
Reset Section/Page
0x nnnn _ nnnn 4.5.2.1/4-37
0x0000_80C0 4.5.2.2/4-39
4.5.2.3/4-40
— —
15
31
CRE
4-37