Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 487

Table 10-29. FPAR Field Descriptions, Large Page Device (ORx[PGS] = 1) (continued)
Bits Name
20 MS Main/spare region locator. In the case that FBCR[BC] = 0, MS is treated as 0.
0 Data is transferred to/from the main region of the FCM buffer; that is, the first 2048 bytes of the buffer
are used as the starting address.
1 Data is transferred to/from the spare region of the FCM buffer; that is, the second 2048 bytes of the
buffer are used as the starting address, but only an initial 64 bytes of spare region are defined.
21–31 CI Column index. CI indexes the first byte to transfer to/from the main or spare region of the NAND Flash
EEPROM and corresponding transfer buffer. In the case that FBCR[BC] = 0, CI is treated as 0. For
MS = 0, CI can range 0x000–0x7FF; for MS = 1, CI can range 0x000–0x03F.
10.3.1.22 Flash Byte Count Register (FBCR)
The local bus Flash byte count register (FBCR), shown in
transfers for reads and writes to the NAND Flash EEPROM.
Offset 0x0_50F4
0
R
W
Table 10-30 describes FBCR fields.
Bits Name
0–19 — Reserved
20–31 BC Byte count determines how many bytes are transferred by the FCM during data read (RB) or data write
(WB) opcodes.
The first byte accessed in the NAND Flash EEPROM is located by the FPAR register, and successive
bytes are transferred until either BC bytes have been counted, or the end of the spare region of the
currently addressed Flash page has been reached.
If BC = 0, an entire Flash page and its spare region will be transferred by FCM, in which case
FPAR[MS] and FPAR[CI] are treated as zero regardless of their values. BC = 0 is the only setting that
permits FCM to generate and check ECC.
10.3.1.23 Flash ECC Block n Register (FECC0–FECC3)
The local bus Flash ECC blockn register (FECCn), shown in
calculated during writes or reads by eLBC. It can be used for verify after write feature in software. Note
that the valid bit sets before the command completion event and hence, the correct ECC could be read
before actual completion of writes/reads.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
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Figure 10-27. Flash Byte Count Register
Table 10-30. FBCR Field Descriptions
Description
Figure 10-27, defines the size of FCM block
19 20
Description
Figure 10-28, specifies the ECC value
Enhanced Local Bus Controller
Access: Read/Write
BC
10-39
31