Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 111

Offset
0x04 Timer 3 and 4 global timers configuration register
(GTCFR2)
0x05–0x0F Reserved
0x10 Timer 1 global timers mode register (GTMDR1)
0x12 Timer 2 global timers mode register (GTMDR2)
0x14 Timer 1 global timers reference register (GTRFR1)
0x16 Timer 2 global timers reference register (GTRFR2)
0x18 Timer 1 global timers capture register (GTCPR1)
0x1A Timer 2 global timers capture register (GTCPR2)
0x1C Timer 1 global timers counter register (GTCNR1)
0x1E Timer 2 global timers counter register (GTCNR2)
0x20 Timer 3 global timers mode register (GTMDR3)
0x22 Timer 4 global timers mode register (GTMDR4)
0x24 Timer 3 global timers reference register (GTRFR3)
0x26 Timer 4 global timers reference register (GTRFR4)
0x28 Timer 3 global timers capture register (GTCPR3)
0x2A Timer 4 global timers capture register (GTCPR4)
0x2C Timer 3 global timers counter register (GTCNR3)
0x2E Timer 4 global timers counter register (GTCNR4)
0x30 Timer 1 global timers event register (GTEVR1)
0x32 Timer 2 global timers event register (GTEVR2)
0x34 Timer 3 global timers event register (GTEVR3)
0x36 Timer 4 global timers event register (GTEVR4)
0x38 Timer 1 global timers prescale register (GTPSR1)
0x3A Timer 2 global timers prescale register (GTPSR2)
0x3C Timer 3 global timers prescale register (GTPSR3)
0x3E Timer 4 global timers prescale register (GTPSR4)
General Purpose (Global) Timer Module 2:
All registers defined for GTM1 are also defined for GTM2; the base address of GTM2 registers is 0x0_06 nn .
0x00 System global interrupt configuration register (SICFR)
0x04 System regular interrupt vector register (SIVCR)
0x08 System internal interrupt pending register (SIPNR_H)
0x0C System internal interrupt pending register (SIPNR_L)
0x10 System internal interrupt group A priority register
(SIPRR_A)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 2-2. Memory Map (continued)
Register
Integrated Programmable Interrupt Controller (IPIC)
Access Reset
R/W 0x00
— —
R/W 0x0000
R/W 0xFFFF
R/W 0x0000
R/W 0x0000
R/W 0x0000
R/W 0xFFFF
R 0x0000
R/W 0x0000
w1c 0x0000
R/W 0x0003
R/W 0x0000_0000
R 0x0000_0000
R 0x0000_0000
R 0x0000_0000
R/W 0x0530_9770
Memory Map
Section/Page
5.7.5.1/5-55
—
5.7.5.2/5-58
5.7.5.3/5-59
5.7.5.4/5-59
5.7.5.5/5-60
5.7.5.2/5-58
5.7.5.3/5-59
5.7.5.4/5-59
5.7.5.5/5-60
5.7.5.6/5-60
5.7.5.7/5-61
8.5.1/8-7
8.5.2/8-9
8.5.3/8-11
8.5.3/8-11
8.5.4/8-13
2-7