Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 155

Table 3-2. MPC8313E Signal Reference by Signal Name (continued)
Name
LSRCID4
LWE0/LFWE/LBS0
LWE1/LBS1
M66EN
MA[0:14]
MBA[0:2]
MCAS
MCK, MCK
MCKE
MCP_OUT
MCS[0:1]
MDM[0:3]
MDQ[0:31]
MDQS[0:3]
MDVAL
MDVAL
MODT[0:1]
MRAS
MSRCID[0:4]
MSRCID0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Functional
Description
Block
Memory debug Debug
source ID 4
eLBC write enable eLBC
0/FCM write enable/
UPM byte (lane)
select 0
eLBC write enable eLBC
1/UPM byte (lane)
select 1
66-MHz system
configuration
DDR address DDR
DDR bank select DDR
DDR column DDR
address strobe
DDR differential DDR
clocks
DDR clock enable DDR
Machine check IPIC
interrupt output
DDR chip select DDR
(2/DIMM)
DDR data mask DDR
DDR data DDR
DDR data strobe DDR
Memory debug data Debug
valid
Memory debug data Debug
valid
DRAM on-die DDR
termination
DDR row address DDR
strobe
Memory debug Debug
source ID 0–4
Memory debug Debug
source ID 0
No. of
I/O
Signals
1 I/O
1 O
1 O
PCI 1 I
15 O
3 O
1 O
2 O
1 O
1 O
2 O
4 O
32 I/O
4 I/O
1 I/O
1 I/O
2 O
1 O
5 I/O
1 I/O
Signal Descriptions
Table/ Alternate
Page Function(s)
10-2/10-5 GTM1_TIN3/
GTM2_TIN4/
GPIO28/SPIMOSI
10-2/10-5 —
10-2/10-5 —
13-3/13-5 —
9-3/9-5 —
9-3/9-5 —
9-3/9-5 —
9-4/9-7 —
9-4/9-7 —
8-2/8-5 —
9-3/9-5 —
9-3/9-5 —
9-3/9-5 —
9-3/9-5 —
10-2/10-5 LA5/GPIO5
10-2/10-5 UART_SIN2/
TSEC_1588_GCLK
9-3/9-5 —
9-3/9-5 —
10-2/10-5 LA[0:4]/GPIO[0:4]
10-2/10-5 UART_SOUT1
3-21