Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 280

System Configuration
Bits Name
28–29 NEXT_STATE
30–31 CURR_STATE
5.8.2.5 Power Management Controller Configuration Register 2 (PMCCR2)
The power management controller configuration register 2 (PMCCR2), shown in
count values used for power-up and power-down timers.
Offset 0x00B10
0 3
R
—
W
Reset 0 0 0 0 0
Figure 5-55. Power Management Controller Configuration Register 2
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
5-72
Table 5-70. PMCCR1 Bit Settings (continued)
Indicate the power state as programmed by the PCI host in PCIPMR1[Power_State]. The host will
write the Power_State bits to request that the device enter a certain low power state. The host may
also write the Power_State to request that the device return to D0 from some low power state. When
the NEXT_STATE field is different than the CURR_STATE field, an interrupt is asserted to the e300
processor through the IPIC. This field is read-only.
00 Host's desired power state is D0
01 Host's desired power state is D1
10 Host's desired power state is D2
11 Host's desired power state is D3 (either D3Hot or D3Warm)
Indicate the current power state of the device. These bits are written by the e300 just before entering
a requested low power state, or when the device has returned to the full on state (D0). Writing these
bits causes the PCIPMR1[Power_State] field to be updated informing the host that the device has
entered the requested power state.
00 Current power state is D0
01 Current power state is D1
10 Current power state is D2
11 Current power state is D3Hot (also used for D3Warm)
4
RCNT
0 0 0 0 0 0 0 0 0 1 0 0 0
Description
15 16 19 20
—
0 0 0 0 0 0 0 0 0 0 0 0 1 0
Figure 5-55, contains
Access: Read/Write
31
PDCNT
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