Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 131

Offset
0x2_4E14 TMR_STAT*—Timestamp status register
0x2_4E18 TMR_CNT_H*—Timer counter high register
0x2_4E1C TMR_CNT_L*—Timer counter low register
0x2_4E20 TMR_ADD*—Timer drift compensation addend register
0x2_4E24 TMR_ACC*—Timer accumulator register
0x2_4E28 TMR_PRSC*—Timer prescale
0x2_4E2C Reserved
0x2_4E30 TMROFF_H*—Timer offset high
0x2_4E34 TMROFF_L*—Timer offset low
0x2_4E40 TMR_ALARM1_H*—Timer alarm 1 high register
0x2_4E44 TMR_ALARM1_L*—Timer alarm 1 high register
0x2_4E48 TMR_ALARM2_H*—Timer alarm 2 high register
0x2_4E4C TMR_ALARM2_L*—Timer alarm 2 high register
0x2_4E50– Reserved
0x2_4E7C
0x2_4E80 TMR_FIPER1*—Timer fixed period interval
0x2_4E84 TMR_FIPER2*—Timer fixed period interval
0x2_4E88 TMR_FIPER*3—Timer fixed period interval
0x2_4EA0 TMR_ETTS1_H*—Timestamp of general purpose external
trigger
0x2_4EA4 TMR_ETTS1_L*—Timestamp of general purpose external
trigger
0x2_4EA8 TMR_ETTS2_H*—Timestamp of general purpose external
trigger
0x2_4EAC TMR_ETTS2_L*—Timestamp of general purpose external
trigger
0x2_4EB0– Reserved
0x2_4FFF
0x2_5000– eTSEC2 REGISTERS
0x2_5FFF
0x3_0000– Reserved, should be cleared
0x3_0FFF
0x3_1008 IMR—Interrupt mask register
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 2-2. Memory Map (continued)
Register
Other eTSECs
15
Security Engine Address Map Registers
Controller Registers
Access Reset
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0002
— —
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0xFFFF_FFFF
R/W 0xFFFF_FFFF
R/W 0xFFFF_FFFF
R/W 0xFFFF_FFFF
— —
R/W 0xFFFF_FFFF
R/W 0xFFFF_FFFF
R/W 0xFFFF_FFFF
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
— —
— —
R/W 0x0000_0000
_0000_0000
Memory Map
Section/Page
15.5.3.10.6/15-116
15.5.3.10.7/15-117
15.5.3.10.7/15-117
15.5.3.10.8/15-117
15.5.3.10.9/15-118
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