Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 495

Option Register Attributes
TRLX EHTR
0 0
0 0
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
1 1
1 1
1
Times in parentheses are specific for the case LCRR[CLKDIV] = 2; other times apply to all CLKDIV values.
10.4.2.2 GPCM Write Signal Timing
The basic GPCM write timing parameters that may be set by the ORn attributes are shown in
The write access cycle commences upon latching of the memory address (LALE negated), and concludes
when LCSn returns high. LBCTL remains stable for the entire cycle to drive data onto any secondary data
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 10-32. GPCM Read Control Signal Timing
XACS ACS t
ARCS
0 0X 0
0 10 ¼
(½)
0 11 ½
1 0X 0
1 10 1
1 11 2
0 0X 0
0 10 ¼
(½)
0 11 ½
1 0X 0
1 10 1
1 11 2
0 0X 0
0 10 1¼
(1½)
0 11 1½
1 0X 0
1 10 2
1 11 3
0 0X 0
0 10 1¼
(1½)
0 11 1½
1 0X 0
1 10 2
1 11 3
Signal Timing (LCLK clock cycles)
t t
CSRP AOE
2+SCY 1
1¾+SCY 1
(2+SCY)
1½+SCY 1
2+SCY 1
1+SCY 1
1+SCY 2
2+SCY 1
1¾+SCY 1
(1½+SCY)
1½+SCY 1
2+SCY 1
1+SCY 1
1+SCY 2
2+2×SCY 1
1¾+2×SCY 2
(1½+2×SCY)
1½+2×SCY 2
2+2×SCY 1
1+2×SCY 2
1+2×SCY 3
2+2×SCY 1
1¾+2×SCY 2
(1½+2×SCY)
1½+2×SCY 2
2+2×SCY 1
1+2×SCY 2
1+2×SCY 3
Enhanced Local Bus Controller
1
t t
OEN RC
0 2+SCY
0 2+SCY
0 2+SCY
0 2+SCY
0 2+SCY
0 3+SCY
1 3+SCY
1 3+SCY
1 3+SCY
1 3+SCY
1 3+SCY
1 4+SCY
4 6+2×SCY
4 7+2×SCY
4 7+2×SCY
4 6+2×SCY
4 7+2×SCY
4 8+2×SCY
8 10+2×SCY
8 11+2×SCY
8 11+2×SCY
8 10+2×SCY
8 11+2×SCY
8 12+2×SCY
Figure 10-35.
10-47