Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 356

e300 Processor Core Overview
• JTAG/debug interface signals—The JTAG (based on the IEEE 1149.1 standard) interface and
debug unit provides a serial interface to the system for performing monitoring and boundary tests.
Two additional signals are added to the e300 core to allow observation of the internal clock state
of the core (stopped) and to allow the external input to force the core into a halted state (ext_halt).
• Core status and control—These signals include the memory reservation signal, machine quiesce
control signals, time base/decrementer clock base enable signal, and the tlbisync signal.
• Clock control—These signals provide for system clock input and frequency control.
• Test interface signals—Signals like address matching, combinational matching, and watchpoint
are used in the core for production testing.
• Transfer attribute signals—These signals provide information about the type of transfer, such as
the transfer size and whether the transaction is bursted, write-through, or cache-inhibited.
7.3.8 Debug Features
Some new debug features are specific to the e300 core. Accesses to the debug facilities are available only
in supervisor mode by using the mtspr and mfspr instructions. The e300 provides the following additional
feature in the JTAG/debug interface: Inclusion of breakpoint status and control pins: stopped and ext_halt.
7.3.8.1 Breakpoint Signaling
The breakpoint signaling provided on the e300 core allows observability of breakpoint matches external
to the core. The iabr, iabr2, dabr, and dabr2 breakpoint signals are asserted for at least one bus clock cycle
when the respective breakpoint occurs. The status of the run state of the e300 core is indicated by the
stopped pin. An asynchronous external breakpoint can be asserted to the e300 core using the ext_halt pin:
• When DBCR and IBCR are configured for an OR combinational signal type, the breakpoint signals
iabr, iabr2 and dabr, dabr2 reflect their respective breakpoints.
• When the DBCR and IBCR are configured for AND combinational signal type, only the iabr2 and
dabr2 breakpoint signals are asserted after the AND condition is met (that is, both instruction
breakpoints occurred or both data breakpoints occurred).
• When the core_stopped pin is asserted, the e300 core has entered a stopped state and all internal
clocking has stopped, indicating that a hardware debug event has occurred.
• The ext_halt input pin can be used to force the core into halted state. The halted state may be a
hardstop, conditional upon the HARDSTOP condition being set through the JTAG/debug interface
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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