Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 196

Reset, Clocking, and Initialization
4.4.1 Clocking in PCI Host Mode
When the device is configured as a PCI host device (RCWH[PCIHOST] = 1), SYS_CLK_IN is the
primary input clock. SYS_CLK_IN feeds the PCI clock divider (÷2) and the PCI_SYNC_OUT and
PCI_CLK_OUT multiplexors. The CFG_CLKIN_DIV configuration input selects whether SYS_CLK_IN
or SYS_CLK_IN/2 is driven out on the PCI_SYNC_OUT and PCI_CLK_OUT signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system.
4.4.1.1 PCI Clock Outputs (PCI_CLK_OUT[0:2])
When the device is configured as a PCI host, it provides three clock output signals, PCI_CLK_OUT[0:2],
for external PCI agents.
When the device comes out of reset, the PCI clock outputs are disabled and are actively driven to a steady
low state. Each of the individual clock outputs can be enabled (enable toggling of the clock) by setting its
corresponding OCCR[PCICOEn] bit. All output clocks are phase aligned to each other and to
PCI_SYNC_OUT.
4.4.2 Clocking In PCI Agent Mode
When the device is configured as a PCI agent, PCI_CLK is the primary input clock. In agent mode, the
SYS_CLK_IN signal may not be used. If it is unused, SYS_CLK_IN should be tied to GND, and the clock
output signals, PCI_CLK_OUTn and PCI_SYNC_OUT, are not used.
In agent mode, the CFG_CLKIN_DIV configuration input can be used to double the internal clock
frequencies, if sampled as 0 during PORESET assertion. This feature is useful if a fixed internal frequency
is desired regardless of whether the PCI clock is running at 33 or 66 MHz. PCI specifications require that
the signal M66EN provides the PCI clock frequency information.
4.4.3 System Clock Domains
As shown in Figure 4-7, the primary clock input (PCI_CLK/PCI_SYNC_IN) frequency is multiplied up
by the system phase-locked loop (PLL) and the clock unit to create three major clock domains:
• The coherent system bus clock (csb_clk)
• The internal clock for the DDR controller (ddr_clk)
• The internal clock for the local bus interface unit (lbc_clk)
The csb_clk frequency is derived from a complex set of factors that can be simplified into the following
equation:
csb_clk = [PCI_SYNC_IN × (1 + ~CFG_CLKIN_DIV)] × SPMF
In PCI host mode, PCI_SYNC_IN × (1 + ~CFG_CLKIN_DIV) is the SYS_CLK_IN frequency.
The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the
csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
4-30 Freescale Semiconductor