Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 815

15.5.3.6.36 Transmit Total Collision Counter (TNCL)
Figure 15-87 describes the definition for the TNCL register.
Offset eTSEC1:0x2_470C; eTSEC2:0x2_570C
0
R
W
Reset
Figure 15-87. Transmit Total Collision Counter Register Definition
Table 15-91 describes the fields of the TNCL register.
Bits Name
0–19 — Reserved
20–31 TNCL Transmit total collision counter. Increments by the number of collisions experienced during the transmission
of a frame as defined as the simultaneous presence of signals on the DO and RD circuits (That is,
transmitting and receiving at the same time). Note: This count does not include collisions that result in an
excessive collision condition.
15.5.3.6.37 Transmit Drop Frame Counter (TDRP)
Figure 15-88 describes the definition for the TDRP register.
Offset eTSEC1:0x2_4714; eTSEC2:0x2_5714
0
R
W
Reset
Figure 15-88. Transmit Drop Frame Counter Register Definition
Table 15-92 describes the fields of the TDRP register.
Bits Name
0–15 — Reserved
16–31 TDRP Transmit drop frame counter. Increments each time a memory error or an underrun has occurred.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
—
All zeros
Table 15-91. TNCL Field Descriptions
—
All zeros
Table 15-92. TDRP Field Descriptions
Enhanced Three-Speed Ethernet Controllers
19 20
Description
15 16
Description
Access: Read/Write
TNCL
Access: Read/Write
TDRP
15-97
31
31