Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 461

10.3.1.2.2 Option Registers (OR
Figure 10-3 shows the bit fields for ORn when the corresponding BRn[MSEL] selects the GPCM machine.
Offset OR0: 0x0_5004
OR1: 0x0_500c
OR2: 0x0_5014
OR3: 0x0_501c
0
R
W
Reset
16 17 18
R
AM —
W
Reset
1
Refer to Table 10-5 for the OR0 reset value. All other option registers have all bits cleared.
Table 10-7 describes OR
Bits Name
0–16 AM GPCM address mask. Masks corresponding BR n bits. Masking address bits independently allows external
devices of different size address ranges to be used. Address mask bits can be set or cleared in any order in
the field, allowing a resource to reside in more than one area of the address map.
0 Corresponding address bits are masked and therefore don't care for address checking.
1 Corresponding address bits are used in the comparison between base and transaction addresses.
17–18 — Reserved
19 BCTLD Buffer control disable. Disables assertion of LBCTL during access to the current memory bank.
0 LBCTL is asserted upon access to the current memory bank.
1 LBCTL is not asserted upon access to the current memory bank.
20 CSNT Chip select negation time. Determines when LCS n and LWE are negated during an external memory write
access handled by the GPCM, provided that ACS ≠ 00 (when ACS = 00, only LWE is affected by the setting
of CSNT). This helps meet address/data hold times for slow memories and peripherals.
0 LCS n and LWE are negated normally.
1 LCS n and LWE are negated earlier depending on the value of LCRR[CLKDIV].
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
)—GPCM Mode
n
19 20 21
BCTLD CSNT ACS
Figure 10-3. Option Registers (OR
fields for GPCM mode.
n
Table 10-7. OR
LCRR
CSNT
[CLKDIV]
x 0 LCS n and LWE are negated normally.
LCS n and LWE are negated normally.
2 1
4 or 8 1 LCS n and LWE are negated one quarter bus clock cycle earlier.
AM
All zeros
22 23 24
XACS SCY
1
All zeros
) in GPCM Mode
n
—
GPCM Field Descriptions
n
Description
Meaning
Enhanced Local Bus Controller
Access: Read/Write
27 28 29 30
SETA TRLX EHTR
15
31
EAD
10-13