Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 789

Bits Name
9–15 Non-Back-to-Back
Inter-Packet-Gap, Part 2
16–23 Minimum IFG
Enforcement
24 —
25–31 Back-to-Back
Inter-Packet-Gap
15.5.3.5.4 Half-Duplex Register (HAFDUP)
The HAFDUP register is written by the user.
Offset eTSEC1:0x2_450C; eTSEC2:0x2_550C
0
R
W
Reset 0 0 0
16
R
Retransmission Maximum
W
Reset 1 1 1
Table 15-43 describes the fields of the HAFDUP register.
Bits Name
0–7 —
8–11 Alternate BEB
Truncation
12 Alt BEB
13 BP No
BackOff
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-42. IPGIFG Field Descriptions (continued)
This is a programmable field representing the non-back-to-back inter-packet-gap in bits. Its
default is 0x60 (96d), which represents the minimum IPG of 96 bits.
This is a programmable field representing the minimum number of bits of IFG to enforce
between frames. A frame is dropped whose IFG is less than that programmed. The default
setting of 0x50 (80d) represents half of the nominal minimum IFG which is 160 bits.
Reserved
This is a programmable field representing the IPG between back-to-back packets. This is
the IPG parameter used exclusively in full-duplex mode and in half-duplex mode if two
transmit packets are sent back-to-back. Set this field to the number of bits of IPG desired.
The default setting of 0x60 (96d) represents the minimum IPG of 96 bits.
Figure 15-39
7
—
0 0 0 0 0
19 20
—
1 0 0 0 0
Figure 15-39. Half-Duplex Register Definition
Table 15-43. HAFDUP Field Descriptions
Reserved
This field is used while ALTERNATE BINARY EXPONENTIAL BACKOFF ENABLE is set. The
value programmed is substituted for the Ethernet standard value of ten. Its default is 0xA.
Alternate binary exponential backoff. This bit is cleared by default.
0 The Tx MAC follows the standard binary exponential back off rule.
1 The Tx MAC uses the ALTERNATE BINARY EXPONENTIAL BACKOFF TRUNCATION setting
instead of the 802.3 standard tenth collision. The standard specifies that any collision after the
tenth uses one less than 210 as the maximum backoff time.
Back pressure no backoff. This bit is cleared by default.
0 The Tx MAC follows the binary exponential back off rule.
1 The Tx MAC immediately re-transmits, following a collision, during back pressure operation.
Enhanced Three-Speed Ethernet Controllers
Description
describes the HAFDUP register.
8 11 12
Alternate BEB
Alt BEB BP No BackOff No BackOff Excess Defer
Truncation
1 0 1 0 0
25 26
0 0 1 1 0
Description
Access: Read/Write
13 14
0 0
Collision Window
1 1
15
1
31
1
15-71