Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 592

PCI Bus Interface
Table 13-3. PCI Interface Signals—Detailed Signal Descriptions (continued)
Signal I/O
PCI_RESET_OUT O
PCI_SERR I/O PCI system error
O
I
PCI_STOP I/O PCI stop.
O
I
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
13-10
PCI reset. This signal is used only in host mode. It should be left unconnected in agent mode.
State Asserted—Devices on the PCI bus are in reset.
Meaning Negated—Devices on the PCI bus operate normally.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Outputs for the bi-directional system error.
State Asserted—An address parity error, a target-abort (when this PCI controller is acting as
Meaning the initiator), or some other system error (where the result is a catastrophic error)
was detected.
Negated—No error.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Inputs for the bi-directional system error.
State Asserted—A device (other than this PCI controller) has detected a catastrophic error.
Meaning Negated—No error.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Outputs for the bi-directional stop.
State Asserted—The PCI controller, acting as a PCI target, is requesting that the initiator stop
Meaning the current transaction.
Negated—The current transaction can continue.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Inputs for the bi-directional stop.
State Asserted—A target is requesting that this PCI controller, as the initiator, stop the current
Meaning transaction.
Negated—The current transaction can continue.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Description
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