Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 595

access to the PCI controller's internal PCI configuration registers. The PCI registers,
PCI_CONFIG_ADDRESS, PCI_CONFIG_DATA, and PCI_INT_ACK, are little endian registers.
13.3.1.1 PCI_CONFIG_ADDRESS
Figure 13-3 shows the PCI_CONFIG_ADDRESS register fields.
Offset 0x0
31 30
R
—
W EN
Reset
The PCI_CONFIG_ADDRESS register holds the address for an access to the PCI configuration space
from the local bus. This register must be programmed before accessing PCI_CONFIG_DATA to perform
the transaction. Only 32-bit accesses are permitted.
If EN=1, BN=0, and DN=0, the access is to the internal PCI configuration registers, so no transaction is
generated on the PCI bus.
If EN=1, BN=0, DN=31, FN=7, and RN=0, writing to PCI_CONFIG_DATA generates a special cycle
transaction and reading from PCI_CONFIG_DATA generates an interrupt acknowledge transaction.
Table 13-6 shows the bit settings of the PCI_CONFIG_ADDRESS register.
Bits Name
31 EN
30–24 —
23–16 BN
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
24 23
BN
Figure 13-3. PCI_CONFIG_ADDRESS Register
Table 13-6. PCI_CONFIG_ADDRESS Field Descriptions
Enable configuration transaction. Determines the type of transaction to be generated.
0 No configuration transaction will be generated by accessing the CONFIG_DATA register. Such an
access will be passed through to the PCI bus as an I/O transaction. Since this is generally not
desirable, the user should not access CONFIG_DATA when the EN bit is 0.
1 A configuration transaction will be generated by accessing the CONFIG_DATA register if BN and
DN are not both zero.
Reserved
Bus number. Specifies the bus segment to which a configuration transaction is directed. If this field
is 0, a Type 0 configuration transaction is generated. Otherwise, a Type 1 configuration transaction
is generated.
16 15 11 10
DN
All zeros
Description
PCI Bus Interface
Access: Write only
8 7
FN RN
2 1 0
—
13-13