Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 228

System Configuration
Bits Name
9 TBEN e300c3 core time base unit enable
0 Time base unit is disabled.
1 Time base unit is enabled.
10–11 COREPR e300c3 core CSB request priority. The priority level for the core in accessing the CSB can be chosen
from 4 possible levels.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority)
12–15 — Reserved. Should be cleared.
16–17 TSEC1588 00 Selects 1588 pins muxed with eTSEC1 (default)
01 Selects 1588 pins muxed with LA[7:15] pads.
10 Selects 1588 pins muxed with UART2 + I2C1 pads.
11 Reserved
18–19 TSECDP eTSEC data priority. Selects the CSB request priority driven by eTSEC1 and eTSEC2 when they
require to transfer data on this bus. The level of priority can be chosen from 4 possible levels.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority)
20–21 TSECBDP eTSEC buffer descriptor priority. Selects the CSB request priority driven by eTSEC1 and eTSEC2
when they require to transfer a buffer descriptor (BD) on this bus. The level of priority can be chosen
from 4 possible levels.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority)
22–23 TSECEP eTSEC emergency priority. Selects the CSB request priority driven by eTSEC1 and eTSEC2 when an
emergency condition occurs. The level of priority can be chosen from 4 possible levels.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority)
24-31 — Reserved, should be cleared.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
5-20
Table 5-26. SPCR Bit Settings (continued)
Table 5-27. CFG_RESET_SRC Values
CFG_RESET_SRC
0000
1000
1001
1010
1011
1100
Description
SPCR[0] SPCR[1]
0
0
0
0
1
1
0
0
1
0
0
0
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