Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 239

5.4.4 WDT Memory Map/Register Definition
The WDT programmable register map occupies 16 bytes of memory-mapped space. Reading undefined
portions of the memory map returns all zeros; writing has no effect.
All WDT registers are 16- or 32-bits wide, located on 16-bit address boundaries, and should be accessed
as 16- or 32-bit quantities. All addresses used in this chapter are offsets from the WDT base, as defined in
Chapter 2, "Memory Map."
Table 5-33 shows the WDT memory map.
Offset
0x0–0x3 Reserved
0x4 System watchdog control register (SWCRR)
0x8 System watchdog count register (SWCNR)
0xC–0xD Reserved
0xE System watchdog service register (SWSRR)
1
SWCRR[SWEN] reset value directly depends on RCWHR[SWEN] (reset configuration word high).
5.4.4.1 System Watchdog Control Register (SWCRR)
The system watchdog control register (SWCRR), shown in
period and configures watchdog timer operation. SWCRR can be read at any time but can be written only
once after system reset.
Offset 0x4
0
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
1
SWCRR[SWEN] reset value directly depends on RCWHR[SWEN] (reset configuration word high).
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 5-33. WDT Register Address Map
Register
SWTC
Figure 5-19. System Watchdog Control Register (SWCRR)
Access
—
R/W
R
—
R/W
Figure 5-19, controls the software watchdog
15 16
—
System Configuration
Reset Value Section/ Page
—
0xFFFF_0003 5.4.4.1/5-31
1
or 0xFFFF_0007
0x0000_FFFF 5.4.4.2/5-32
—
0x0000 5.4.4.3/5-33
Access: Read/Write
28 29 30
SWEN SWRI SWPR
1
0 1
—
—
31
1
5-31