Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 186

Reset, Clocking, and Initialization
4.3.2.2.6 eTSEC2 Mode
The eTSEC2 mode reset configuration word field, shown in
eTSEC2 controller (enhanced three-speed Ethernet controller interface).
Reset Configuration
Word High Register
(RCWHR) Bits
19–21
The reset value of the system I/O configuration register high (SICRH)
depends on the setting of TSEC2M. This is used to avoid contention in
systems not using TBI or RTBI modes. In non-TBI modes, device signals
which have additional functions are set to be in a non-TSEC function, thus
not driven during and after reset. The function of these signals can be
changed by writing to this register during system initialization. See
Section 5.3.2.6, "System I/O Configuration Register High (SICRH)."
4.3.2.2.7 e300 Core True Little-Endian
The true little endian reset configuration word field, shown in
operates in big-endian mode or true little-endian mode at reset.
Reset Configuration
Word High Register
(RCWHR) Bit
28
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
4-20
Table 4-17. eTSEC2 Mode Configuration
Value
Field Name
(Binary)
TSEC2M 000
001
010
011
100
101
110
111
Table 4-18. e300 Core True Little-Endian
Value
Field Name
(Binary)
TLE 0
1
Table 4-17, selects the protocol used by the
The eTSEC2 controller operates in the MII protocol, using only four
transmit data signals and four receive data signals.
The eTSEC2 controller operates in the RMII protocol, using only two
transmit data signals and two receive data signals.
Reserved
The eTSEC2 controller operates in the RGMII protocol, using four
transmit data signals and four receive data signals.
Reserved
The eTSEC2 controller operates in the RTBI protocol, using only four
transmit data signals and four receive data signals.
The eTSEC2 controller operates in the SGMII protocol, using the
on-chip PHY.
Reserved
NOTE
Table 4-18, selects whether the e300 core
Big-endian mode
True little-endian mode
Meaning
Meaning
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