Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 795

Bits Name
22 Excess Defer Excessive transmission defer. This bit latches high and is cleared when read. This bit is cleared by
default.
0 Normal operation.
1 The MAC excessively defers a transmission.
23–31 — Reserved
15.5.3.5.13 MAC Station Address Part 1 Register (MACSTNADDR1)
The MACSTNADDR1 register is written by the user. The value of the station address written into
MACSTNADDR1 and MACSTNADDR2 is byte reversed from how it would appear in the DA field of a
frame in memory. For example, for a station address of 0x12345678ABCD, MACSTNADDR1 is set to
0xCDAB7856 and MACSTNADDR2 is set to 0x34120000.
Figure 15-48 shows the MACSTNADDR1 register.
Offset eTSEC1:0x2_4540; eTSEC2:0x2_5540
0
R
Station Address, 6th Octet
W
Reset
Table 15-52 describes the fields of the MACSTNADDR1 register.
Bit
0–7 Station Address, 6th Octet
8–15 Station Address, 5th Octet
16–23 Station Address, 4th Octet
24–31 Station Address, 3rd Octet
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-51. IFSTAT Field Descriptions (continued)
7 8
Station Address, 5th Octet
Figure 15-48. MAC Station Address Part 1 Register Definition
Table 15-52. MACSTNADDR1 Field Descriptions
Name
This field holds the sixth octet of the station address. The sixth
octet (station address bits 40
This field holds the fifth octet of the station address. The fifth octet
(station address bits 32
This field holds the fourth octet of the station address. The fourth
octet (station address bits 24
This field holds the third octet of the station address. The third
octet (station address bits 16
Enhanced Three-Speed Ethernet Controllers
Description
15 16
Station Address, 4th Octet
All zeros
Description
–
47) defaults to a value of 0x0.
–
39) defaults to a value of 0x0.
–
31) defaults to a value of 0x0.
–
23) defaults to a value of 0x0.
Access: Read/Write
23 24
Station Address, 3rd Octet
15-77
31