Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 386

Integrated Programmable Interrupt Controller (IPIC)
Note that in core disabled mode the user should use SIVCR only read an updated interrupt vector (SMVCR
should not be used).
Offset 0x64
0
R
MVECx
W
Reset
Figure 8-24. System Management Interrupt Vector Register (SMVCR)
Table 8-30 defines the bit fields of SMVCR.
Bits Name
0–5 MVECx Backward (MPC8260) compatible system management interrupt vector. Specifies a 6-bit unique number of the
IPIC's highest priority system management interrupt source, pending to the core. When a system management
interrupt request occurs, SMVCR can be read. If there are multiple system management interrupt sources,
SMVCR latches the highest priority system management interrupt. Note that MVECx f correctly reflects only
the first 64 interrupt vectors (See
The value of SMVEC cannot change while it is being read.
6–24 — Write ignored, read = 0
25–31 MVEC System management interrupt vector. Specifies a 7-bit unique number of the IPIC's highest priority system
management interrupt source, pending to the core. When a system management interrupt request occurs,
SMVCR can be read. If there are multiple system management interrupt sources, SMVCR latches the highest
priority system management interrupt. Note that MVEC field will correctly reflect all interrupt vectors (See
Table 8-6
The value of SMVEC cannot change while it is being read.
8.6 Functional Description
The following sections describe the types of interrupts, interrupt configurations, and their priorities.
8.6.1 Interrupt Types
The IPIC is responsible for receiving hardware-generated interrupts from different sources (both internal
and external) along with prioritizing and delivering them to the CPU for servicing. The interrupt sources
are controlled by the IPIC unit and may cause three types of exceptions in the processor core. The int signal
is the main interrupt output from the IPIC to the processor core and causes the external interrupt
exception.The cint signal is the critical interrupt output from the IPIC to the processor core and causes the
critical external interrupt exception. The smi signal is the system management interrupt output from the
IPIC to the processor core and causes the system management interrupt exception. The machine check
exception is caused by the internal mcp signal generated by the IPIC, informing the processor of error
conditions, assertion of the external MCP request, and other conditions.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
8-28
5 6
Table 8-30. SMVCR Field Descriptions
Table 8-6
for details).
—
All zeros
Description
for details).
Access: Read only
24 25 31
MVEC
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