Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 326

e300 Processor Core Overview
7.1.3.3 Load/Store Unit (LSU)
The LSU executes all load and store instructions and provides the data transfer interface between the
GPRs, FPRs, and the cache/memory subsystem. The LSU calculates effective addresses, performs data
alignment, and provides sequencing for load/store string and multiple instructions.
Load and store instructions are issued and executed in program order; however, the memory accesses can
occur out of order. Synchronizing instructions are provided to enforce strict ordering.
Cacheable loads, when free of data bus dependencies, can execute out of order with a maximum
throughput of one per cycle and with a two-cycle total latency. Data returned from the cache is held in a
rename register until the completion logic commits the value to a GPR or FPR. Stores cannot be executed
in a predicted manner and are held in the store queue until the completion logic signals that the store
operation is to be completed to memory. The core executes store instructions with a maximum throughput
of one per cycle and with a three-cycle total latency. The time required to perform the actual load or store
depends on whether the operation involves the cache, system memory, or an I/O device.
7.1.3.4 System Register Unit (SRU)
The SRU executes various system-level instructions, including condition register logical operations and
move to/from special-purpose register instructions. It also executes integer add/compare instructions. In
order to maintain system state, most instructions executed by the SRU are completion-serialized; that is,
the instruction is held for execution in the SRU until all prior instructions issued have completed. Results
from completion-serialized instructions executed by the SRU are not available or forwarded for
subsequent instructions until they complete.
7.1.4 Completion Unit
The completion unit tracks instructions in program order from dispatch through execution and then
completes. Completing an instruction commits the core to any architectural register changes caused by that
instruction. In-order completion ensures the correct architectural state when the core must recover from a
mispredicted branch or an interrupt.
Instruction state and other information required for completion is kept in a five-entry FIFO completion
queue. A single completion queue entry is allocated for each instruction once it enters the execution unit
from the dispatch unit. An available completion queue entry is a required resource for dispatch; if no
completion entry is available, dispatch stalls. A maximum of two instructions per cycle are completed in
order from the queue.
7.1.5 Memory Subsystem Support
The core provides separate instruction and data caches and MMUs. The core also provides an efficient
processor bus interface to facilitate access to main memory and other bus subsystems. The memory
subsystem support functions are described in the following sections.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
7-8 Freescale Semiconductor