Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 536

Enhanced Local Bus Controller
slow memory device is delayed by the number of clock cycles specified in the OR
any existing bus turnaround cycle.
10.5 Initialization/Application Information
10.5.1 Interfacing to Peripherals in Different Address Modes
This section provides guidelines for interfacing to peripherals.
10.5.1.1 Multiplexed Address/Data Bus for 26-Bit Addressing
In this mode, the eLBC is used with port sizes of 8 and 16 bits; address bits A[6:21] will appear on
LAD[0:15] (with zero bits on LAD[16:31]) during address phases, while the lower 10 bits of the address,
A[22:31], are driven permanently on LA[16:25]. The connection is illustrated in
Local Bus Interface
LAD[0:15]
LA[16:25]
Figure 10-69. Multiplexed Address/Data Bus for 26-Bit Addressing
10.5.1.2 Non-Multiplexed Address and Data Buses
For small address space applications the address latch may be eliminated entirely if the local bus address
is taken entirely from LA[0:25], in which case addresses driven onto LAD during address phases are
simply ignored. The connection is illustrated in
remain the same except that few things need not be taken care of like ASHIFT parameter, LAD bus
turnaround time, LALE timings etc.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-88
D
LAD[0:15]
LE
LALE
Muxed Address/Data
Unmuxed Address
Q
Latch
Figure 10-70. In non-multiplexed mode, waveforms etc
register in addition to
n
Figure 10-69.
Device
D[15:0]
A[21:6]
A[31:22]
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